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PDF K4P4G304EC Data sheet ( Hoja de datos )
| Número de pieza | K4P4G304EC | |
| Descripción | 4Gb DDP LPDDR2-S4 SDRAM | |
| Fabricantes | Samsung | |
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Rev. 0.5, Sep. 2010
K4P4G304EC
Preliminary
4Gb DDP LPDDR2-S4 SDRAM
134FBGA, 11x11.5, 2/CS, 2CKE
64M x32 + 64M x32
datasheet
http://www.DataSheet4U.com/
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
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1 page  
K4P4G304EC-FGC1
Preliminary Rev. 0.5
datasheet LPDDR2-S4 SDRAM
LPDDR2-S4 SDRAM SPECIFICATION
4G = 64M x 32 + 64M x 32 (8M x 32 x 8 banks + 8M x 32 x 8 banks) 2/CS, 2CKE
1.0 KEY FEATURE
• Double-data rate architecture; two data transfers per clock cycle
• Bidirectional data strobes (DQS, DQS), These are transmitted/received with data to be used in capturing data at the receiver
• Differential clock inputs (CK and CK)
• Differential data strobes (DQS and DQS)
• Commands & addresses entered on both positive and negative CK edges; data and data mask referenced to both edges of DQS
• 8 internal banks for concurrent operation
• Data mask (DM) for write data
• Burst Length: 4 (default), 8 or 16
• Burst Type: Sequential or Interleave
• Read & Write latency : Refer to Table 47 LPDDR2 AC Timing Table
• Auto Precharge option for each burst access
• Configurable Drive Strength
• Auto Refresh and Self Refresh Modes
• Partial Array Self Refresh and Temperature Compensated Self Refresh
• Deep Power Down Mode
• HSUL_12 compatible inputs
• VDD1/VDD2/VDDQ/VDDCA
: 1.8V/1.2V/1.2V/1.2V
• No DLL : CK to DQS is not synchronized
• Edge aligned data output, center aligned data input
• Auto refresh duty cycle : 3.9us
• 2/CS, 2CKE
2.0 ORDERING INFORMATION
Part No.
K4P4G304EC-FGC1
Org.
x32
Package
11x11.5 134FBGA
(Lead Free, Halogen Free)
Temperature
http://www.DataSheet4U.com/
Tc=-25~85’C
NOTE :
1) K4P4G304EC-% : VDD1=1.8V, VDD2=1.2V, VDDQ=1.2V, VDDCA=1.2V
Max Frequency
800Mbps (tCK=2.50ns)
Interface
HSUL_12
-5-
5 Page 
K4P4G304EC-FGC1
Preliminary Rev. 0.5
datasheet LPDDR2-S4 SDRAM
5.0 FUNCTIONAL DESCRIPTION
This device contains the following number of bits:
4Gb has 2,147,483,648 bits + 2,147,483,648 bits
LPDDR2-S4 uses a double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus
contains command, address, and Bank information. Each command uses one clock cycle, during which command information is transferred on both the
positive and negative edge of the clock.
LPDDR2-S4 uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 4n
prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the
LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in
a programmed sequence.
For LPDDR2-S4 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address
and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered
coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.
Prior to normal operation, the LPDDR2 must be initialized.
http://www.DataSheet4U.com/
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