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PDF NCV8876 Data sheet ( Hoja de datos )
| Número de pieza | NCV8876 | |
| Descripción | Automotive Grade Start-Stop Non-Synchronous Boost Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV8876
Automotive Grade
Start-Stop Non-Synchronous
Boost Controller
The NCV8876 is a Non-Synchronous Boost controller designed to
supply a minimum output voltage during Start-Stop vehicle operation
battery voltage sags. The controller drives an external N-channel
MOSFET. The device uses peak current mode control with internal
slope compensation. The IC incorporates an internal regulator that
supplies charge to the gate driver.
Protection features include, cycle-by-cycle current limiting,
protection and thermal shutdown.
Additional features include low quiescent current sleep mode
operation. The NCV8876 is enabled when the supply voltage drops
below 7.3 V, with boost operation initiated when the supply voltage is
below 6.8 V.
Features
• Automatic Enable Below 7.3 V (Factory Programmable)
• Boost Mode Operation at 6.8 V
• $2% Output Accuracy Over Temperature Range
• Peak Current Mode Control with Internal Slope Compensation
• Externally Adjustable Frequency Operation
• Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump
• Low Quiescent Current in Sleep Mode (<11 mA Typical)
• Cycle−by−Cycle Current Limit Protection
• Hiccup−Mode Overcurrent Protection (OCP)
• Thermal Shutdown (TSD)
• This is a Pb−Free Device
Typical Applications
• Applications Requiring Regulated Voltage through Cranking and
Start−Stop Operation
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
8876xx
ALYW
G
1
8876xx = Specific Device Code
xx = 00, 01
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
STATUS 1
ISNS 2
GND 3
GDRV 4
8 ROSC
7 VC
6 VOUT
5 VDRV
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV887600D1R2G SOIC−8 2500 / Tape &
(Pb−Free)
Reel
NCV887601D1R2G SOIC−8 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 12
1
Publication Order Number:
NCV8876/D
1 page  
NCV8876
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min Typ Max Unit
GATE DRIVER (Note 3)
Driving Voltage Source Current
Backdrive Diode Voltage Drop
Driving Voltage
Idrv VOUT − VDRV = 1 V
35 45
− mA
Vd,bd
VDRV – VOUT, Id,bd = 5 mA
− − 0.7 V
VDRV
IVDRV = 0.1 − 25 mA
NCV887600 5.8 6.0 6.2
NCV887601 5.8 6.0 6.2
V
UVLO
Undervoltage Lock−out,
Threshold Voltage
Vuvlo,fall
VOUT falling
3.4 3.59 3.8
V
Undervoltage Lock−out
THERMAL SHUTDOWN
Vuvlo,rise VOUT rising
3.90 4.05 4.20
V
Thermal Shutdown Threshold
(Note 2)
Tsd TJ rising
160 170 180
°C
Thermal Shutdown Hysteresis
(Note 2)
Tsd,hys
TJ falling
10 15 20 °C
Thermal Shutdown Delay (Note 2)
VOLTAGE REGULATION
tsd,dly
From TJ > Tsd to stop switching
− − 100 ns
Voltage Regulation
VOUT,reg
NCV887600 6.66 6.8 6.94
NCV887601 6.66 6.8 6.94
V
Threshold IC Enable
VOUT descending
NCV887600 7.1 7.3 7.5
NCV887601 7.1 7.3 7.5
V
Threshold IC Disable
VOUT ascending
NCV887600 7.5 7.7 7.9
NCV887601 7.5 7.7 7.9
V
Threshold IC Enable – Voltage
Regulation
NCV887600 0.32
NCV887601 0.32
0.5
0.5
−
−
V
Threshold IC Disable – Threshold
IC Enable
NCV887600
−
0.4
−
NCV887601
−
0.4
−
V
2. Not tested in production. Limits are guaranteed by design.
3. An RGND = 15 kW GDRV−GND resistor is strongly recommended.
www.onsemi.com
5
5 Page 
NCV8876
The maximum power dissipation in the diode can be
calculated as follows:
PD + Vf (max) IOUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
The 4 amp, 40 V NRVB440MFS SO−8FL package
Schottky diode is a recommended device.
10. Design Notes
• VOUT serves a dual purpose (feedback and IC power).
The VDRV circuit has a current pulse power draw
resulting in current flow from the output sense location
to the IC. Trace ESL will cause voltage ripple to
develop at IC pin VOUT which could affect
performance.
♦ Use a 1 mF IC VOUT pin decoupling capacitor close
to IC in addition to the VDRV decoupling capacitor.
• Classic feedback loop measurements are not possible
(VOUT pin serves a dual purpose as a feedback path
and IC power). Feedback loop computer modeling
recommended.
♦ A step load test for stability verification is
recommended.
• Compensation ground must be dedicated and connected
directly to IC ground.
♦ Do not use vias. Use a dedicated ground trace.
• ROSC programming resistor ground must be dedicated
and connected directly to IC ground
♦ Do not use vias. Use a dedicated ground trace.
• IC ground & current sense resistor ground sense point
must be located on the same side of PCB.
♦ Vias introduce sufficient ESR/ESL voltage drop
which can degrade the accuracy of the current
feedback signal amplitude (signal bounce) and
should be avoided.
• Star ground should be located at IC ground pad.
VIN rL L
♦ This is the location for connecting the compensation
and current sense grounds.
• The IC architecture has a leading edge ISNS blanking
circuit. In some instances, current pulse leading edge
current spike RC filter may be required.
♦ If required, 120 pF + 750 W are a recommended
evaluation starting point.
11. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC−VC signal if R2 is of similar order of magnitude as RESD.
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type−I compensation is not possible due to the presence
of RESD. The Figure 13 compensation network corresponds
to a Type−II network in series with RESD. The resulting
control−output transfer function is an accurate mathematical
model of the IC in a boost converter topology. The model
does have limitations and a more accurate SPICE model
should be considered for a more detailed analysis:
• The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
• The efficiency term h should be a reasonable operating
condition estimate.
Vd VOUT
VC
R2
C2
C1
RESD
VCTRL
R0
OTA
VREF
GDRV
ISNS
R1
RLOW
Rds(on)
RGDRV
Ri
VOUT
rCf
COUT
ROUT
GND
Figure 13. NCV8876 OTA and Compensation
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11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCV8876.PDF ] | |
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