PDF M2GL005 Data sheet ( Hoja de datos )

Número de pieza	M2GL005
Descripción	IGLOO2 FPGAs
Fabricantes	Microsemi
Logotipo
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No Preview Available ! IGLOO2 FPGAs Revision 0 Introduction Microsemi’s IGLOO®2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable, and the most secure programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and math blocks for digital signal processing (DSP). High speed serial interfaces include PCI EXPRESS® (PCIe®), 10 Gbps attachment unit interface (XAUI)/XGMII extended sublayer (XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high speed memory interfaces. IGLOO2 Device Status Family Devices M2GL005 M2GL010T/M2GL010 M2GL025T/M2GL025 M2GL050T M2GL050 M2GL090T/M2GL090 M2GL100T/M2GL100 M2GL150T/M2GL150 http://www.DataSheet4U.net/ Status Advance Advance Advance Advance Advance Advance Advance IGLOO2 Product Brief and Pin Descriptions The product brief and pin descriptions are published separately: IGLOO2 Product Brief IGLOO2 Pin Descriptions June 2013 © 2013 Microsemi Corporation 1 datasheet pdf - http://www.DataSheet4U.net/ 1 page IGLOO2 FPGAs Datasheet PCI/PCI-X DC Voltage Specification – Applicable to MSIO Bank ONLY . . . . . . . . . . . . . . . . . . . . . . . . . 37 PCI/PCI-X Minimum and Maximum AC Input and Output Levels – Applicable to MSIO Bank ONLY . . . 37 AC Switching Characteristics for Receiver (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 38 HSTL DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 HSTL Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HSTL Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 HSTL Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DDR1/SSTL2 DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DDR1/SSTL2 Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DDR1/SSTL2 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DDR1/SSTL2 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SSTL18 DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SSTL18 Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DDR2/SSTL18 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DDR2/SSTL18 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SSTL15 Minimum and Maximum AC Input and Output Levels (for DDRIO I/O Bank Only) . . . . . . . . . . . 52 DDR3/SSTL15 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DDR3/SSTL15 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LPDDR DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LPDDR Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LPDDR Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LPDDR Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LVDS DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LVDS Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LVDS25 Receiver Characteristics . . . . . . . . . . . . . . . . . . .http://www.DataSheet4U.net/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LVDS25 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LVDS33 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LVDS33 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 B-LVDS DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 B-LVDS Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 AC Switching Characteristics for Receiver (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 59 M-LVDS DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 M-LVDS Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AC Switching Characteristics for Receiver (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 60 Mini-LVDS DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Mini-LVDS Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 AC Switching Characteristics for Receiver (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 62 RSDS DC Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 RSDS Minimum and Maximum AC Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 AC Switching Characteristics for Receiver (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 64 LVPECL DC Voltage Specification – Applicable to MSIO I/O Banks Only . . . . . . . . . . . . . . . . . . . . . . . . 65 LVPECL Minimum and Maximum AC Input and Output Levels – Applicable to MSIO I/O Banks Only . . 65 LVPECL Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Data Enable Register Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision 0 5 datasheet pdf - http://www.DataSheet4U.net/ 5 Page ADVANCE INFORMATION (Subject to Change) IGLOO2 FPGAs Datasheet Table 3 • FPGA and Embedded Flash Programming, Storage, and Operating Limits Product Grade Storage Temperature Programming Temperature Element Grade Programming Cycles Commercial Min. TJ = 0°C Max. TJ = 85°C Min. TJ = 0°C Max. TJ = 85°C Min. TJ = 0°C Max. TJ = 85°C FPGA Embedded flash 500 < 1,000 < 10,000 Industrial Min. TJ = –40°C Max. TJ = 100°C Min. TJ = 0°C Max. TJ = 85°C Min. TJ = –40°C Max. TJ = 100°C FPGA Embedded flash 500 < 1,000 < 10,000 Retention 20 years 20 years 10 years 20 years 20 years 10 years Thermal Characteristics Introduction The temperature variable in the Microsemi SoC Products Group Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power. JA = T----J----P–-----T----A- JB = http://www.DataSheet4U.net/ T----J----P–-----T----B- EQ 1 JC = T----J----–P-----T----C- where JA = Junction-to-air thermal resistance JB = Junction-to-board thermal resistance JC = Junction-to-case thermal resistance TJ = Junction temperature TA = Ambient temperature TB = Board temperature (measured 1.0 mm away from the package edge) TC = Case temperature P = Total power dissipated by the device EQ 2 EQ 3 Revision 0 11 datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
M2GL005	IGLOO2 FPGAs	Microsemi

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