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PDF GD25Q80 Data sheet ( Hoja de datos )
| Número de pieza | GD25Q80 | |
| Descripción | 8Mbit Dual and Quad SPI Flash | |
| Fabricantes | GigaDevice | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GD25Q80 (archivo pdf) en la parte inferior de esta página. Total 34 Páginas | ||
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Uniform Sector
8Mbit Dual and Quad SPI Flash
GD25Q80
FEATURES
◆ 8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
◆ Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
◆ Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.2/0.28/0.6s typical
-Chip Erase time: 5s typical
◆ Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
◆ Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
◆ Software/Hardware Write Protection
◆ Advanced security Features(1)
-Write protect all/portion of memory via software
-16-Bit Customer ID
-Enable/Disable protection with WP# Pin
-Security Architecture
-Top or Bottom, Sector or Block selection
◆ Single Power Supply Voltage
◆ Minimum 100,000 Program/Erase Cycles
-Full voltage range:2.7~3.6V
Note: 1.Please contact Gigadevice for details
http://www.DataSheet4U.net/
GENERAL DESCRIPTION
The GD25Q80 (8M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8–LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Uniform Sector
8Mbit Dual and Quad SPI Flash
GD25Q80
Data Protection
The GD25Q80 provide the following data protection methods:
◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1. GD25Q80 Protected area size
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
XX0 0 0
00001
00010
00011
00100
01001
01010
01011
01100
0X101
XX1 1X
10001
10010
10011
1010X
11001
11010
11011
1110X
Blocks
NONE
15
14 to 15
12 to 15
8 to 15
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 15
15
15
15
15
0
0
0
0
Addresses
NONE
0F0000H-0FFFFFH
0E0000H-0FFFFFHhttp://www.DataSheet4U.net/
0C0000H-0FFFFFH
080000H-0FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-0FFFFFH
0FF000H-0FFFFFH
0FE000H-0FFFFFH
0FC000H-0FFFFFH
0F8000H-0FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Density
NONE
64KB
128KB
256KB
512KB
64KB
128KB
256KB
512KB
1M
1M
4KB
8KB
16KB
32KB
4KB
8KB
16KB
32KB
Portion
NONE
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
ALL
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
5
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Uniform Sector
8Mbit Dual and Quad SPI Flash
GD25Q80
Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure7. Read Data Bytes at Higher Speed Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
24-bit address
SI
0B
23 22 21
3210
SO High-Z
CS#
SCLK
SI
SO
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210
Data Out1
Data Out2
76543210765
MSB
MSB
Dual Output Fast Read (3BH)
http://www.DataSheet4U.net/
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure8. Dual Output Fast Read Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI
SO
CS#
SCLK
SI
SO
Command
3B
High-Z
24-bit address
23 22 21
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
64206420
Data Out1 Data Out2
75317531
MSB
MSB
6
7
11
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet GD25Q80.PDF ] | |
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