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PDF HD66206 Data sheet ( Hoja de datos )
| Número de pieza | HD66206 | |
| Descripción | 80-Channel Column/Common Driver | |
| Fabricantes | hitachi semiconductor | |
| Logotipo |  |
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HD66206
(80-Channel Column/Common Driver for Middle- or Large-sized
Liquid Crystal Panel)
Rev 0.2
February 1996
Description
The HD66206 is an 80-channel LCD driver, which is used for liquid crystal dot matrix display. This
product can drive various types of liquid crystal displays, from small-sized to monochrome VGA-sized
displays. Since this product can function as a column and a common driver, an LCD panel can be
configured only with this product.
Features
• Logic power supply voltage: 2.7 to 5.5V
• Display duty: 1/16 (1/5 bias) to 1/240
• 80 liquid crystal display drive circuits
• Liquid crystal display drive voltage: 6 to 28V
• Data transfer speed
8 MHz max (at 5-V operation)
6.5 MHz max (at 3-V operation)
• Chip enable signal automatic generation
• Standby function
• Controllers that can be used with
HD64645/HD64646 (LCTC series)
HD66841 (LVIC series)
• Packages
TFP-100B
No package (bare chip)
• CMOS process
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1 page  
HD66206
Block Functions
Liquid crystal display drive circuit
Generates one of four levels V1 to V4 to the output pin to drive the liquid crystal display according to the
combination of data of the 80-bit latch circuit and the M signal.
80-bit latch circuit
Latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of
CL1, and transmits it to the liquid crystal display drive circuit.
80-bit bi-directional shift register (also used as a latch circuit)
When FCS is low, this register functions as an 80-bit shift register. At this time, D0L and D1R are used
as data input/output pins. When FCS is high, this register functions as a 20 × 4-bit unit latch circuit. At
this time, data that is input in parallel to data input pin D0L, D1R, D2 and D3 is converted to 4-bit data,
and then is latched to this register according to the latch signal generated by the selector.
Data conversion circuit
When FCS is low, D0L and D1R are used as data input/output pins. When FCS is high, D0L, D1R, D2,
and D3 are input data.
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Selector
Decodes output data from the counter and generates a latch signal. Functions when latching data at
serial-latch operation (when FCS is high). At this time, after 80 bits of data Y1 to Y80 are completely
latched, the operation of the selector terminates. Even if input data changes, data in the latch circuit is
maintained.
Operating mode switching circuit
Switches common driver operation (when FCS is low) and column driver operation (when FCS is high).
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5 Page 
HD66206
CL2
D0L
D1R
D2
D3
CAR
(the first IC)
CL1
Y1
(the first IC)
Y80
(the first IC)
12 3 4
----------
seg.4 seg.8 seg.12 seg.16 ----------
seg.3 seg.7 seg.11 seg.15 ----------
seg.2 seg.6 seg.10 seg.14 ----------
seg.1 seg.5 seg.9 seg.13 ----------
19 20 21 22 23
-----------------------
seg.76 seg.80 seg.84 seg.88 seg.92 -----------------------
seg.75 seg.79 seg.83 seg.87 seg.91 -----------------------
seg.74 seg.78 seg.82 seg.86 seg.90 -----------------------
seg.73 seg.77 seg.81 seg.85 seg.89 -----------------------
The next IC is activated.
156 157 158 159 160
seg.624 seg.628 seg.632 seg.636 seg.640
seg.623 seg.627 seg.631 seg.635 seg.639
seg.622 seg.626 seg.630 seg.634 seg.638
seg.621 seg.625 seg.629 seg.633 seg.637
SEG.80
SEG.1
Figure 8 Timing Charts for Application Example in Column Driver Operation
CL1
FLM
M
12 3 4
237 238 239 240 1 2 3 4
237 238 239 240
-------------------
-------------------
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Y80
(the first IC) V4
V2
V3
Y79 V3
(the first IC) V4
V2
V3
V1
V4
V1
V4
V4
Figure 9 Timing Charts for Application Example in Common Driver Operation
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11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet HD66206.PDF ] | |
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