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PDF A1359 Data sheet ( Hoja de datos )
| Número de pieza | A1359 | |
| Descripción | Factory-Programmed Dual Output Linear Hall Effect Sensor IC | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Features and Benefits
• Dual tracking outputs: analog voltage output and pulse
width modulated (PWM) output
• Matched analog and PWM outputs enable user to detect
various output error conditions
• Factory-programmed offset, sensitivity, and polarity
• Sensitivity temperature coefficient (TC) and QVO/QD
temperature coefficient programmed at Allegro™ for
improved accuracy
• High speed chopping scheme minimizes quiescent voltage
output (QVO) drift across temperature
• Temperature-stable QVO and sensitivity
• Output voltage clamps provide short circuit diagnostic
capabilities
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Enhanced EMC performance for stringent automotive
applications
Package: 8-pin TSSOP (suffix LE)
surface mount
Description
New applications for linear output Hall effect sensors, such
as displacement and angular position, require high accuracy
in conjunction with redundant outputs. The Allegro A1359
programmable, linear, Hall effect sensor IC has been designed
specifically to achieve both goals. The features associated
with this linear device make it ideal for use in automotive
and industrial applications requiring high accuracy, and
this temperature-stable device operates across an extended
temperature range: –40°C to 150°C.
The accuracy of the device is enhanced via programmability
at the Allegro factory for optimization of device sensitivity,
the quiescent voltage output (QVO: output with no magnetic
field), and quiescent duty cycle (QD) for a given application or
circuit. The A1359 also allows optimized performance across
the entire operating temperature range via programming the
temperature coefficients for both sensitivity and QVO/QD at
Allegro end-of-line test. This ratiometric Hall effect sensor IC
provides a analog voltage, and a PWM signal with duty cycle,
that are proportional to the applied magnetic field.
Each BiCMOS monolithic circuit integrates a Hall element,
temperature-compensating circuitry to reduce the intrinsic
sensitivity drift of the Hall element, a small-signal high-gain
Not to scale
Continued on the next page…
VSUPPLY
VCC
CBYPASS
100 nF
Functional Block Diagram
Chopper
Switches
Amp
Signal
Recovery
Signal
Conditioning
Low-Pass
Filter
Sensitivity, QVO, and
Temperature Compensation
PWM
Frequency Trim
PWM Carrier
Generation
Mismatch
Compensation
VOUT
RPULLUP
PWMOUT
GND
A1359-DS, Rev. 1
1 page  
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA, CBYPASS = 0.1 μF , VCC = 5 V,
unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
PWM Output Characteristics (continued)
Load Resistance3,6
RPULLUP
Load Capacitance3,6
CL
Duty Cycle Jitter3
JitterPWM
PWMOUT to VCC
PWMOUT to GND
Measured over 1000 PWM output clock periods,
3 sigma values, Sens = 9 mV/G
2000
–
–
–
–
±0.18
–
10
–
Ω
nF
%D
Quiescent Voltage Output (QVO)
Quiescent Voltage Output
Quiescent Voltage Output
Equivalent PWM
VOUT(Q)
D(Q)
TA = 25°C
TA = 25°C, VCC = 4.5 to 5.5 V
2.45 2.5 2.55
49 50 51
V
%D
PWM Carrier Frequency
Carrier Frequency
Sensitivity
Sensitivity Temperature Coefficient
fPWM
TA = 25°C
TCSENS
Programmed at TA = 150°C, calculated relative
to Sens at 25°C
3.6
0.08
4
0.12
4.4
0.16
kHz
%/°C
Analog Sensitivity7
Error Components
PWM to Analog Output Mismatch8
Linearity Sensitivity Error9
Symmetry Sensitivity Error9
Ratiometry Quiescent Voltage
Output Error10
Ratiometry Sensitivity Error9
Ratiometry Clamp Error10
Quiescent Voltage Output Drift Through
Temperature Range
A1359LLETR-T
Sen
B = ±125 G, TA = 25°C
A1359LLETR-RP-T B = ±125 G, TA = 25°C
VOUTERR
1.75 V < VOUT < 3.25 V
VOUT = 1.25 V, VOUT = 3.75 V
LinERR
SymERR
RatVOUT(Q)
Across supply voltage range,
(relative to VCC = 5 V)
RatSens
Across supply voltage range,
(relative to VCC = 5 V)
RatVOUTCLP
TA = 25°C, across supply voltage range, (relative
to VCC = 5 V)
∆VOUT(Q) TA =150°C
8.73
–9.27
–57.4
–85
–
–
–
–
–
–17
9.0
–9.0
–
–
±0.5
±0.5
±0.5
±0.5
±0.5
–
9.27
–8.73
+57.4
+85
–
–
–
–
–
+17
mV/G
mV/G
mV
mV
%
%
%
%
%
mV
Sensitivity Drift Due to Package
Hysteresis
∆SensPKG TA = 25°C, after temperature cycling
– ±2 –
%
11 G (gauss) = 0.1 mT (millitesla).
2At power-up, the output is held low until VCC exceeds VUVLOHI. When the device reaches the operational power level, the output remains valid until
VCC drops below VUVLOLO, when the output is pulled low.
3Determined by design and characterization, not evaluated at final test.
4fc varies as much as approximately ±20% across the full operating ambient temperature range and process.
5VCLPL and VCLPH scale with VCC , due to ratiometry.
6Load capacitance and resistance directly effects the rise time of the PWM output by tr = 0.35 × 2 × π × RL× CL.
7Room temperature sensitivity can drift, ΔSensLIFE , by an additional 3% (typical worst case) over the life of the product.
8See Characteristic Definitions section.
9Applicable to both analog and PWM channels. Tested at Allegro factory for only the analog channel, and determined by design and characterization
for the PWM channel.
10Applies only to the analog channel.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A1359
Factory-Programmed Dual Output Linear Hall Effect Sensor IC
With Analog and Pulse Width Modulated Outputs
Package LE, 8-Pin TSSOP
3.00±0.10
8
6.40 BSC 4.40±0.10
A
D
2.20 D
E
12
1.50
D
8X
0.10 C
0.30
0.19
0.65 BSC
Branded Face
SEATING
PLANE
C
1.10 MAX
0.15
0.05
For Reference Only; not for tooling use (reference MO-153 AA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference land pattern layout (reference IPC7351 SOP65P640X110-8M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias can improve
thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Branding scale and appearance at supplier discretion
D Hall element, not to scale
E Active Area Depth 0.36 mm REF
8º
0º
0.20
0.09
0.45
8
1.70
0.65
0.60
+0.15
–0.10
1.00 REF
6.10
0.25 BSC
SEATING PLANE
GAUGE PLANE
12
B PCB Layout Reference View
1
A1359LLETR-T
1
A1359LLETR-RP-T
C Branding Reference View
Top line is device designator
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet A1359.PDF ] | |
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