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PDF ADAU1977 Data sheet ( Hoja de datos )
| Número de pieza | ADAU1977 | |
| Descripción | Quad ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad ADC with Diagnostics
ADAU1977
FEATURES
GENERAL DESCRIPTION
Programmable microphone bias (5 V to 9 V) with diagnostics
Four 10 V rms capable direct-coupled differential inputs
On-chip PLL for master clock
Low EMI design
106 dB ADC dynamic range
−95 dB THD + N
Selectable digital high-pass filter
24-bit ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I2C/SPI control
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S justified, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation system
The ADAU1977 incorporates four high performance analog-to-
digital converters (ADCs) with direct-coupledinputs capable of
10 V rms. The ADC usesmultibitsigma-delta(Σ-Δ) architecture
with continuous time frontend for low EMI. The ADCscan be
connected to the electret microphone (ECM) directly and pro-
vide the bias for powering the microphone. Built-in diagnostic
circuitry detects faults on input linesand includescomprehensive
diagnostics for faults on microphone inputs. The faults reported
are short to battery, short to microphone bias, short to ground,
short between positive and negative input pins, and open input
terminals. In addition, each diagnostic fault is available as an
IRQ flag for ease in system design. An I2C/SPI control port is
also included. The ADAU1977 uses only a single 3.3 V supply.
The part internally generatesthe microphone bias voltage.The
microphone bias is programmable in a few stepsfrom 5 V to 9 V.
The low power architecture reducesthe power consumption.
An on-chip PLL can derive the master clock from an external
clock input or frame clock (sample rate clock). When fed with
a frame clock, the PLL eliminates the need fora separate high
frequency master clock in the system. The ADAU1977 is
available in a 40-lead LFCSP package.
http://www.DataSheet4U.net/
FUNCTIONAL BLOCK DIAGRAM
MICBIAS
MB_GND
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
5V TO 9V
PROG
BIAS
BOOST
CONVERTER
IOUT 50mA
PGND
ADC
ADC
ADC
ADC
VBAT
AGND1 AGND3
AVDDx
AVDD2
DIAGNOSTICS
BG
REF
PLL
AGND2
AGNDx
AGND2
ADAU1977
3.3V TO 1.8V
REGULATOR
DVDD
I2C/SPI
CONTROL
IOVDD
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CL ATCH
FAULT
PD/RST
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility isassumedby AnalogDevicesforits use,norforany infringements of patents orother
rights of thirdparties thatmay resultfrom its use.Specificationssubjecttochangewithoutnotice.No
license is granted by implicationor otherwise underany patentorpatentrights of AnalogDevices .
Trademarks andregistered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Data Sheet
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 3.
Parameter
INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage Current
Input Capacitance
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Test Conditions/Comments
IOH = 1 mA
IOL = 1 mA
ADAU1977
Min Max Unit
0.7 × IOVDD
0.3 × IOVDD
±10
5
V
V
µA
pF
IOVDD − 0.60
0.4
V
V
POWER SUPPLY SPECIFICATIONS
L = 4.7 µH, AVDDx = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, fS = 48 kHz (master mode), unless otherwise noted.
Table 4.
Parameter
DVDD
AVDDx
IOVDD
VBAT1
IOVDD Current
Normal Operation
Power-Down
AVDDx Current
Normal Operation
Power-Down
Boost Converter Current
Normal Operation
Power-Down
DVDD Current
Normal Operation
Power-Down
VBAT Current
Normal Operation
Power-Down
POWER DISSIPATION
Normal Operation
AVDDx
Power-Down, All Supplies
Test Conditions/Comments
On-chip LDO
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
http://www.DataSheet4U.net/
fS = 48 kHz to 192 kHz
Min Typ Max Unit
1.62 1.8
1.98 V
3.0 3.3 3.6 V
1.62 3.3 3.6 V
14.4 18
V
450 µA
880 µA
1.75 mA
20 µA
Boost off, 4-channel ADC, DVDD internal
Boost on, 4-channel ADC, DVDD internal
Boost off, 4-channel ADC, DVDD external
Boost on, 4-channel ADC, DVDD external
14 mA
14.5 mA
9.6 mA
10.1 mA
270 µA
Boost on, 4-channel ADC, MICBIAS = 8.5 V, no load
Boost on, 4-channel ADC, MICBIAS = 8.5 V, 42 mA
34
168
180
mA
mA
µA
DVDD external = 1.8 V
VBAT = 14.4 V
4.5 mA
65 µA
575 625 µA
575 625 µA
Master clock = 256 fS, 48 kHz
DVDD internal, MICBIAS = 8.5 V at 42 mA load
PD/RST pin held low
265 mW
9 mW
1 When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault.
Rev. 0 | Page 5 of 64
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Data Sheet
ADAU1977
Pin No.
31
32
33
34
35
36
37
38
39
40
Mnemonic
AVDD3
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
AVDD1
EP
In/Out1
P
I
I
I
I
I
I
I
I
P
Description
Analog Power Supply. Connect this pin to an analog 3.3 V supply.
Analog Input Channel 1 Inverting Input.
Analog Input Channel 1 Noninverting Input.
Analog Input Channel 2 Inverting Input.
Analog Input Channel 2 Noninverting Input.
Analog Input Channel 3 Inverting Input.
Analog Input Channel 3 Noninverting Input.
Analog Input Channel 4 Inverting Input.
Analog Input Channel 4 Noninverting Input.
Analog Power Supply. Connect this pin to an analog 3.3 V supply.
Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit
board (PCB).
1 I = input, O = output, I/O = input/output, and P= power.
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Rev. 0 | Page 11 of 64
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