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PDF ADAU1966 Data sheet ( Hoja de datos )

Número de pieza ADAU1966
Descripción 16-Channel High Performance
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! ADAU1966 Hoja de datos, Descripción, Manual

16-Channel High Performance
Differential Output, 192 kHz, 24-Bit DAC
ADAU1966
FEATURES
118 dB DAC dynamic range and SNR
−98 dB THD + N
Differential voltage DAC output
2.5 V digital and 3.3 V or 5 V analog and IO supplies
299 mW total (19 mW/channel) quiescent power at AVDD = 3.3 V
PLL generated or direct MCLK master clock
Low EMI design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout ±3°C accuracy
SPI and I2C controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes with up to 16-channel input/output
80-lead LQFP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Home theater systems
Digital audio effects processors
GENERAL DESCRIPTION
The ADAU1966 is a high performance, single-chip DAC that
provides 16 digital-to-analog converters (DACs) with differen-
tial output using the Analog Devices, Inc., patented multibit
sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included,
allowing a microcontroller to adjust volume and many other
parameters. The ADAU1966 operates from 2.5 V digital and
3.3 V or 5 V analog supplies. A linear regulator is included to
generate the digital supply voltage from the analog supply volt-
age. The ADAU1966 is available in an 80-lead LQFP package.
The ADAU1966 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock
from an external LRCLK, the ADAU1966 can eliminate the
need for a separate high frequency master clock and can be
used with or without a bit clock. The DACs are designed using
the latest Analog Devices continuous time architectures to
further minimize EMI. By using 2.5 V digital supplies, power
consumption is minimized, and the digital waveforms are a
smaller amplitude, further reducing emissions.
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FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
ADAU1966
DAC
DAC
DAC
DAC
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
PRECISION
VOLTAGE
REFERENCE
SERIAL DATA PORT
SDATA
IN
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
SPI/I2C
CONTROL PORT
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
DAC
DAC
DAC
DAC
INTERNAL
TEMP
SENSOR
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
datasheet pdf - http://www.DataSheet4U.net/

1 page




ADAU1966 pdf
ADAU1966
Parameter
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
Test Conditions/Comments
TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
VSUPPLY pin
VSENSE pin
1 Functionally guaranteed at −40°C to +125°C case temperature.
Min Typ
1.50
1.43 1.50
1.50
3.0 5
2.26 2.50
Max Unit
V
1.56 V
V
5.5 V
2.59 V
Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 105°C, unless otherwise noted.
Table 4.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
Conditions/Comments
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running
Eight channels running
AVDDx = 3.3 V
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TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
VSUPPLY pin
VSENSE pin
Min Typ
Max Unit
108 109
110 112
−85
−92
−92
2.00 (5.66)
−10
−25 −6
−30
100
0
0.375
95.25
100
1.50
1.43 1.50
1.50
3.0 5
2.25 2.50
dB
dB
dB
dB
−83 dB
V rms (V p-p)
+10 %
+25 mV
+30 ppm/°C
dB
Degrees
dB
dB
±0.6 dB
Ω
V
1.56 V
V
5.5 V
2.55 V
1 Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 5.
Parameter
Transconductance, TA = 25°C
Transconductance, TA = 105°C
Min
6.4
5.2
Typ
7 to 10
7.5 to 8.5
Max
14
12
Unit
mmhos
mmhos
Rev. 0 | Page 5 of 52
datasheet pdf - http://www.DataSheet4U.net/

5 Page





ADAU1966 arduino
Pin No.
22, 39
23
24
25
27
28
31
32
33
34
35
36
37
38
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Type 1
PWR
I
O
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I/O
I
I
I
I
GND
PWR
O
O
O
O
O
O
O
O
PWR
I
I
GND
O
Mnemonic
IOVDD
VSENSE
VDRIVE
VSUPPLY
DBCLK
DLRCLK
DSDATA8/SA
DSDATA7/SA
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
CDATA/ADDR1/SA
COUT/SDA/SA
CCLK/SCL/SA
CLATCH/ADDR0/SA
SA_MODE
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
O TS_REF
O DAC5P
O DAC5N
O DAC6P
O DAC6N
O DAC7P
O DAC7N
O DAC8P
ADAU1966
Description
Power for Digital Input and Output Pins, 3.3 V to 5 V.
2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Drive for Base of Pass Transistor.
5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Bit Clock for DACs.
Frame Clock for DACs.
DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Control Data Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 15).
Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Control Clock Input (SPI)/Control Clock Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 15).
Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (highhttp://www.DataSheet4U.net/ active, see Table 15 and Table 16).
Power-Up/Reset (Low Active).
Analog Ground.
Analog Power.
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple with 470 nF to AVDD2.
DAC Bias 2. AC couple with 470 nF to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with
100 nF to AGND2.
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
DAC7 Positive Output.
DAC7 Negative Output.
DAC8 Positive Output.
Rev. 0 | Page 11 of 52
datasheet pdf - http://www.DataSheet4U.net/

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