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PDF AD5144 Data sheet ( Hoja de datos )
| Número de pieza | AD5144 | |
| Descripción | (AD5124 / AD5144) Nonvolatile Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad Channel, 128-/256-Position, I2C/SPI,
Nonvolatile Digital Potentiometer
AD5124/AD5144/AD5144A
FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
4 mm × 4 mm package option
4 kV ESD protection
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
LRDAC
POWER-ON
RESET
AD5124/AD5144
RDAC1
INPUT
REGISTER 1
RESET
DIS
SCLK/SCL
SDI/SDA
SYNC/ADDR0
SDO/ADDR1
SERIAL
INTERFACE 7/8
RDAC2
INPUT
REGISTER 2
RDAC3
INPUT
REGISTER 3
RDAC4
INPUT
REGISTER 4
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
A3
W3
B3
A4
W4
B4
GND VSS
WP
Figure 1. AD5124/AD5144 24-Lead LFCSP
GENERAL DESCRIPTION
The AD5124/AD5144/AD5144A potentiometers provide a
nonvolatile solution for 128-/256-position adjustment applications,
offering guaranteed low resistor tolerance errors of ±8% and up to
±6 mA current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these devices
suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allow for pin-to-pin connection.
The wiper values can be set through an SPI-/I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
www.DataSheet.net/ The AD5124/AD5144/AD5144A are available in a compact,
24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts
are guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Table 1. Family Models
Model
Channel Position
AD51231 Quad
128
AD5124 Quad
128
AD5124 Quad
128
AD51431 Quad
256
AD5144 Quad
256
AD5144 Quad
256
AD5144A Quad
256
AD5122 Dual
128
AD5122A Dual
128
AD5142 Dual
256
AD5142A Dual
256
AD5121 Single
128
AD5141 Single
256
Interface
I2C
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
1 Two potentiometers and two rheostats.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Data Sheet
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Terminal Voltage Range5
Capacitance A, Capacitance B3
Symbol
IA, IB, and IW
CA, CB
Capacitance W3
CW
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
VINH
VINL
VHYST
IIN
CIN
VOH
VOL
IDD
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
AD5124/AD5144/AD5144A
Test Conditions/Comments Min
Typ1 Max
Unit
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
−6
−1.5
VSS
−500
+6
+1.5
VDD
25
12
12
5
±15 +500
mA
mA
V
pF
pF
pF
pF
nA
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
www.DataSheet.net/
VSS = GND
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = VDD ± 10%,
code = full scale
0.8 × VLOGIC
0.7 × VLOGIC
0.1 × VLOGIC
5
0.2 × VLOGIC
±1
V
V
V
V
µA
pF
VLOGIC
0.4
V
V
0.6 V
−1 +1 µA
2 pF
2.3
±2.25
1.8
2.25
−5.5
5.5
±2.75
VDD
VDD
0.7 5.5
400
−0.7
2
320
1 120
3.5
−66 −60
V
V
V
V
µA
nA
µA
mA
µA
nA
µW
dB
Rev. 0 | Page 5 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Data Sheet
AD5124/AD5144/AD5144A
Parameter1
t12
tSP3
Test Conditions/Comments
Standard mode
Fast mode
Fast mode
Min
20 + 0.1 CL
0
Typ Max
300
300
50
Unit Description
ns Fall time of SCL signal, tFCL
ns
ns Pulse width of suppressed spike
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter
Min Typ Max Unit Description
t1
t2
t3
tEEPROM_PROGRAM1
tEEPROM_READBACK
t2
POWER_UP
tRESET
1 µs End command to LRDAC falling edge
50 ns Minimum LRDAC low time
0.1 10 µs RESET low time
15 50 ms Memory program time (not shown in Figure 8)
7 30 µs Memory readback time (not shown in Figure 8)
75 µs Start-up time (not shown in Figure 8)
30 µs Reset EEPROM restore time (not shown in Figure 8)
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8 DB7
DB0 (LSB)
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
www.DataSheet.net/
CONTROL BITS
DATA BITS
ADDRESS BITS
Figure 4. Input Shift Register Contents
SCL
t6
SDA
t7
PS
t11
t2
t4
t12
t1
t3
t6
t5
t10
S
Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence)
t8
t9
P
Rev. 0 | Page 11 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet AD5144.PDF ] | |
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