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PDF AD9550 Data sheet ( Hoja de datos )
| Número de pieza | AD9550 | |
| Descripción | Integer-N Clock Translator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Integer-N Clock Translator
for Wireline Communications
AD9550
FEATURES
Converts preset standard input frequencies to standard
output frequencies
Input frequencies from 8 kHz to 200 MHz
Output frequencies up to 810 MHz LVPECL and LVDS
(200 MHz CMOS)
Preset pin-programmable frequency translation ratios
On-chip VCO
Single-ended CMOS reference input
Two output clocks (independently programmable as LVDS,
LVPECL, or CMOS)
Single supply (3.3 V)
Very low power: <450 mW (under most conditions)
Small package size (5 mm × 5 mm)
Exceeds Telcordia GR-253-CORE jitter generation, transfer
and tolerance specifications
BASIC BLOCK DIAGRAM
REF
PLL
OUTPUT
CIRCUITRY
PIN DECODER
AD9550
Figure 1.
OUT2
OUT1
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Flexible frequency translation for wireline applications such
as Ethernet, T1/E1, SONET/SDH, GPON, xDSL
Wireless infrastructure
Test and measurement (including handheld devices)
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GENERAL DESCRIPTION
The AD9550 is a phase-locked loop (PLL) based clock translator
designed to address the needs of wireline communication and
base station applications. The device employs an integer-N PLL
to accommodate the applicable frequency translation requirements.
It accepts a single-ended input reference signal at the REF input.
The AD9550 is pin programmable, providing a matrix of
standard input/output frequency translations from a list of
15 possible input frequencies to a list of 52 possible output
frequency pairs (OUT1 and OUT2).
The AD9550 output is compatible with LVPECL, LVDS, or
single-ended CMOS logic levels, although the AD9550 is
implemented in a strictly CMOS process.
The AD9550 operates over the extended industrial temperature
range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
AD9550
Parameter
CMOS MODE
Output Voltage High, VOH
IOH = 10 mA
IOH = 1 mA
Output Voltage Low, VOL
IOL = 10 mA
IOL = 1 mA
Frequency Range
Min Typ
2.8
2.8
0
Duty Cycle
45
Rise/Fall Time1 (20% to 80%)
500
1 The listed values are for the slower edge (rise or fall).
JITTER CHARACTERISTICS
Table 3.
Parameter
JITTER GENERATION
Output
12 kHz to 20 MHz
LVPECL
Min Typ Max
1.31
1.28
0.89
LVDS Output
CMOS Output
1.32
1.29
1.24
1.26
50 kHz to 80 MHz
LVPECL
0.44
0.75
0.58
LVDS
CMOS
0.45
0.76
0.39
0.44
JITTER TRANSFER BANDWIDTH
Bandwidth Setting
Low
Medium
High
JITTER TRANSFER PEAKING
Bandwidth Setting
Low
Medium
High
170
20
75
1.3
0
0.08
Max Unit Test Conditions/Comments
Output driver static
V
V
Output driver static
0.5 V
0.3 V
200 MHz 3.3 V CMOS; output toggle rates in excess of the
maximum are possible, but with reduced amplitude
(see Figure 14)
55 % At maximum output frequency
745 ps 3.3 V CMOS; 10 pF load
Unit Test Conditions/Comments
ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz
ps rms Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5
to Pin Y0 = 111111 (see Figure 3)
ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz
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ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding
CMOS toggle rates above 250 MHz
Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz
ps rms Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5
to Pin Y0 = 111111 (see Figure 3)
ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz
ps rms Input = 122.88 MHz, output = 155.52 MHz
ps rms Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding
CMOS toggle rates above 250 MHz
See the Typical Performance Characteristics section
Hz
kHz
kHz
See the Typical Performance Characteristics section
dB
dB
dB
Rev. 0 | Page 5 of 20
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
AD9550
3.3V DIFFERENTIAL
OUTPUT
(LVDS OR
LVPECL MODE)
0.1µF
HIGH
IMPEDANCE
INPUT
0.1µF
DOWNSTREAM
DEVICE
AD9550
3.3V DIFFERENTIAL
OUTPUT
(LVDS OR
LVPECL MODE)
AD9550
DOWNSTREAM
DEVICE
Figure 21. AC-Coupled LVDS or LVPECL Output Driver
Figure 22. DC-Coupled LVDS or LVPECL Output Driver
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Rev. 0 | Page 11 of 20
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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