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PDF PCA9629 Data sheet ( Hoja de datos )

Número de pieza PCA9629
Descripción Fm+ I2C-bus stepper motor controller
Fabricantes NXP Semiconductors　
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PCA9629
Fm+ I2C-bus stepper motor controller
Rev. 1 — 29 February 2012
Product data sheet
1. General description
The PCA9629 is an I2C-bus controlled low-power CMOS device that provides all the logic
and control required to drive a four phase stepper motor. PCA9629 is intended to be used
with external high current drivers to drive the motor coils. The PCA9629 supports three
stepper motor drive formats: one-phase (wave drive), two-phase, and half-step. In
addition, when used as inputs, four General Purpose Input/Outputs (GPIOs) allow sensing
of logic level output from optical interrupter modules and generate active LOW interrupt
signal on the INT pin of PCA9629. This is a useful feature in sensing home position of
motor shaft or reference for step pulses. Upon interrupt, the PCA9629 can be
programmed to automatically stop the motor or reverse the direction of rotation of motor.
Output wave train is programmable using control registers. The control registers are
programmed via the I2C-bus. Features built into the PCA9629 provide highly flexible
control of stepper motor, off-load bus master/micro and significantly reduce I2C-bus traffic.
These include control of step size, number of steps per single command, number of full
rotations and direction of rotation. A ramp-up on start and/or ramp-down on stop is also
provided.
The PCA9629 is available in a 16-pin TSSOP package and is specified over the 40 C to
+85 C industrial temperature range.
2. Features and benefits
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Generate motor coil drive phase sequence signals with four outputs for use with
external high current drivers to off-load CPU
Four balanced push-pull type outputs capable of sinking 25 mA or sourcing 25 mA for
glueless connection to external high current drivers needed to drive motor coils
Up to 1000 pF loads with 100 ns rise and fall times
Built-in oscillator requires no external components
Stepper motor drive control logic
One-phase (wave drive), two-phase, and half-step drive format logic level outputs
Programmable step rate: 344.8 kpps to 0.3 pps with 5 % accuracy
Programmable ramp-up on start and ramp-down to stop
Programmable steps and rotation control
Sensor enabled drive control: linked to interrupt from I/O pins
Direction control of motor shaft
Selectable active hold, power off or released states for motor shaft
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PCA9629 pdf
NXP Semiconductors
PCA9629
Fm+ I2C-bus stepper motor controller
7. Functional description
Refer to Figure 1 “PCA9629 block diagram”.
7.1 Device address
Following a START condition, the bus master must send the target slave address followed
by a read or write operation. The slave address of the PCA9629 is shown in Figure 3.
Slave address pins AD1 and AD0 choose one of 16 slave addresses. To conserve power,
no internal pull-up resistors are incorporated on AD1 and AD0. Table 4 shows all 16 slave
addresses by connecting the AD0 and AD1 to VDD, VSS, SCL or SDA.
slave address
0 1 0 A3 A2 A1 A0 R/W
fixed
programmable
002aad905
Fig 3. PCA9629 device address
The last bit of the first byte defines the reading from or writing to the PCA9629. When set
to logic 1 a read is selected, while logic 0 selects a write operation.
Table 4. PCA9629 address map
AD1
AD0
Device family high-order Variable portion of address
address bits
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A6 A5 A4 A3 A2 A1 A0
VSS VSS 0 1 0 0 0 0 0
VSS VDD 0 1 0 0 0 0 1
VDD
VSS
0
1
0
0
0
1
0
VDD
VDD
0
1
0
0
0
1
1
VSS SCL 0 1 0 0 1 0 0
VSS SDA 0 1 0 0 1 0 1
VDD SCL 0 1 0 0 1 1 0
VDD SDA 0 1 0 0 1 1 1
SCL
VSS
0
1
0
1
0
0
0
SDA
VSS
0
1
0
1
0
0
1
SCL
VDD
0
1
0
1
0
1
0
SDA
VDD
0
1
0
1
0
1
1
SCL SCL 0 1 0 1 1 0 0
SCL SDA 0 1 0 1 1 0 1
SDA SCL 0 1 0 1 1 1 0
SDA SDA 0 1 0 1 1 1 1
Address
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
PCA9629
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 February 2012
© NXP B.V. 2012. All rights reserved.
5 of 51
Datasheet pdf - http://www.DataSheet4U.co.kr/

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PCA9629 arduino
NXP Semiconductors
PCA9629
Fm+ I2C-bus stepper motor controller
7.3.4.2 WDCNTL — WatchDog Control register
Table 10. WDMOD - Watchdog control register (address 06h) bit description
Legend: * default value.
Address Register Bit Access Value Description
06h WDCNTL 7:5 read only 000* Reserved.
4 write only 1
Clear WDINT flag.
0* Read value.
3 read only 1
WDINT: watchdog interrupt flag set.[1]
0* WDINT: watchdog interrupt flag not set.
2 read only 1
WDRST: watchdog reset flag.[2]
0* WDRST: watchdog reset flag not set.
1 R/W
1 WDMOD: watchdog interrupt and reset mode
(set only).
0* WDMOD: watchdog interrupt only mode.
0 R/W
1 WDEN: watchdog enabled (set only).
0* WDEN: watchdog disabled.
[1] Use bit 4 to clear this bit.
[2] Reading WDCNTL register clears this bit.
This register controls the operation of the watchdog timer. Watchdog timer can be enabled
by setting the WDEN bit of this register. WDEN is a set-only bit. Once set (enabled), this
bit cannot be cleared by software. It can be cleared only with a hardware reset or
watchdog reset.
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The WDMOD bit determines the mode of operation. This bit is a set-only bit. There are
two modes of operation:
• Interrupt only mode: This is the default mode of operation. In this mode, when the
watchdog timer times out, the interrupt flag is set (WDINT) and an interrupt is
generated to the host controller.
• Interrupt and reset mode: In this mode, when the watchdog timer times out, the reset
flag is set (WDRST) and an interrupt is generated to host controller and resets the
chip to POR state.
WDINT flag: This flag can be cleared by writing a ‘1’ to bit 4 of this register.
WDRST flag: This flag indicates that a watchdog reset has occurred. This flag does not
get cleared by the watchdog reset. After a watchdog reset event, the host controller can
read this bit to determine if a reset had occurred. The WDRST flag gets cleared after it is
read or after an external reset is applied.
Before enabling the watchdog timer, the watchdog flags (interrupt flag and reset flag)
must be cleared (if they are set). The interrupt flag is cleared by using bit 4 of the
WDCNTL register and the reset flag is cleared just by reading the WCNTL register.
PCA9629
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 February 2012
© NXP B.V. 2012. All rights reserved.
11 of 51
Datasheet pdf - http://www.DataSheet4U.co.kr/

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