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PDF L6393 Data sheet ( Hoja de datos )
| Número de pieza | L6393 | |
| Descripción | Half-bridge gate driver | |
| Fabricantes | STMicroelectronics | |
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L6393
Features
■ High voltage rail up to 600 V
■ dV/dt immunity ± 50 V/nsec in full temperature
range
■ Driver current capability:
– 270 mA source,
– 430 mA sink
■ Switching times 75/35 nsec rise/fall with 1 nF
load
■ 3.3 V, 5 V CMOS/TTL inputs comparators with
hysteresys
■ Integrated bootstrap diode
■ Uncommitted comparator
■ Adjustable dead-time
■ Compact and simplified layout
■ Bill of material reduction
■ Flexible, easy and fast design
Application
Motor driver for home appliances, factory
automation, industrial drives and fans. HID
ballasts, power supply units.
Half-bridge gate driver
Preliminary Data
SO-14
DIP-14
Description
The L6393 is a high-voltage device manufactured
with the BCD "OFF-LINE" technology. It has a
monolithic half-bridge gate driver for N-channel
Power MOSFET or IGBT.
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The high side (floating) section is designed to
stand a voltage rail up to 600 V.
The logic inputs are CMOS/TTL compatible down
to 3.3 V for easy of interfacing µC/DSP.
The IC embeds an uncommited comparator
available for protections against over-current,
over-temperature, etc.
Table 1. Device summary
Order codes
L6393
L6393D
L6393D013TR
Package
DIP-14
SO-14
SO-14
Packaging
Tube
Tube
Tape and reel
March 2008
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation.
Details are subject to change without notice.
1/20
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20
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
L6393
3
Truth table
Truth table
Note:
Table 3.
Truth table
INPUTS
OUTPUTS
SD
PHASE
BRAKE
LVG
L XX L
HL LH
HLHH
HHL H
HHH L
HVG
L
L
L
L
H
X: don’t care
In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and
the resulting signal is in phase with the high side output HVG and in opposition of phase with
the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal
drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG
output. If BRAKE is set to low level the low side output LVG is always ON and the high side
output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides
the possibility to control the power stages using the PHASE signal to select the current
direction in the bridge and the BRAKE signal to perform current slow decay on the low sides.
From the point of view of the logic operations the two signals PHASE and BRAKE are
completely equivalent, that means the two signals can be exchanged without any change in
the behavior on the resulting output signals (see the Block Diagram in Fig.1).
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Note: the dead time between the turn OFF of one power switch and the turn ON of the other
power switch is defined by the resistor connected between DT pin and the ground.
5/20
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
L6393
Electrical characteristics
Table 8. DC opereation electrical characteristics (VCC = 15 V; TJ = +25 °C) (continued)
Symbol Pin
Parameter
Test condition
Min Typ Max Unit
Driving buffers section
Iso
High/low side source short
circuit current
VIN = Vih (tp < 10 µs)
10, 13
Isi
High/low side sink short
circuit current
VIN = Vil (tp < 10 µs)
Logic inputs
Vil
Vih
IPHASEh
IPHASEl
IBRAKEh
IBRAKEl
ISDh
ISDl
Low level logic threshold
voltage
1, 2, 3
High level logic threshold
voltage
PHASE logic “1” input bias
current
PHASE = 15 V
1
PHASE logic “0” input bias
current
PHASE = 0 V
BRAKE logic “1” input bias
current
BRAKE = 15 V
3
BRAKE logic “0” input bias
current
BRAKE = 0 V
SD logic “1” input bias
current
2
SD logic “0” input bias
current
SD = 15 V
SD = 0 V
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2.21
1. RDSon is tested in the following way:
RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
270
430
175
175
30
0.83
260
1
260
1
100
1
mA
mA
V
V
µA
µA
µA
µA
µA
µA
Table 9.
Symbol
Vio
Iib
Vol
Sense comparator
Pin Parameter
Input offset voltage
8, 9
Input bias current
6
Open drain low level
Output voltage
td_comp
SR
Comparator delay
6 Slew rate
Test conditions
Iod = - 3 mA
CPOUT pulled to 5 V
through 100kΩ resistor
CL = 180 nF, Rpu = 5 kΩ
Min Typ Max Unit
±10 TBD mV
1 µA
0.5 V
110 210
ns
TBD
V/µs
11/20
Datasheet pdf - http://www.DataSheet4U.co.kr/
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet L6393.PDF ] | |
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