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PDF 74HC4543 Data sheet ( Hoja de datos )

Número de pieza 74HC4543
Descripción BCD to 7-segment latch/decoder/driver
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! 74HC4543 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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74HC/HCT4543
BCD to 7-segment
latch/decoder/driver for LCDs
Product specification
File under Integrated Circuits, IC06
December 1990
Datasheet pdf - http://www.DataSheet4U.co.kr/

1 page




74HC4543 pdf
Philips Semiconductors
BCD to 7-segment latch/decoder/driver for
LCDs
Product specification
74HC/HCT4543
www.DataSheet.net/
Fig.6 Logic diagram.
Fig.7 Display.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
For RATINGS see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, standard outputs.
December 1990
5
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5 Page





74HC4543 arduino
Philips Semiconductors
BCD to 7-segment latch/decoder/driver for
LCDs
AC WAVEFORMS
Product specification
74HC/HCT4543
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the address input (Dn)
to output (Qn) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing the latch disable input
(LD) to output (Qn) propagation delays and
the output transition times.
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(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the blanking (BI) to
output (Qn) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing the address (Dn) to
latch disable (LD) input set-up and hold
times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
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