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PDF AD5686 Data sheet ( Hoja de datos )
| Número de pieza | AD5686 | |
| Descripción | (AD5684 / AD5686) 16-/12-Bit nanoDAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad, 16-/12-Bit nanoDAC+
with SPI Interface
AD5686/AD5684
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5686/AD5684, members of the nanoDAC+™ family, are
low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm
× 3 mm LFCSP and a TSSOP package.
The AD5686/AD5684 also incorporate a power-on reset circuit
and a RSTSEL pin that ensures that the DAC outputs power up
to zero scale or midscale and remain at that level until a valid
write takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 μA at 3 V while in power-down mode.
The AD5686/AD5684 employ a versatile SPI interface that
operates at clock rates up to 50 MHz, and all devices contain
a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
SCLK
SYNC
SDIN
SDO
VDD GND
AD5686/AD5684
VREF
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN
×1/×2
LDAC RESET
RSTSEL
Figure 1.
GAIN
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
www.DataSheet.net/
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI Internal AD5686R
SPI External AD5686
I2C Internal AD5696R
I2C External AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5686 (16-bit): ±2 LSB maximum
AD5684 (12-bit): ±1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Data Sheet
AD5686/AD5684
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.1
Table 3.
Parameter2
Output Voltage Settling Time
AD5686
AD5684
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
SNR
SFDR
SINAD
Min Typ Max
58
57
0.8
0.5
0.13
500
0.1
0.2
0.3
−80
100
6
90
83
80
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
4 Digitally generated sine wave @ 1 kHz.
Unit
µs
µs
V/µs
nV-sec
nV-sec
kHz
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
Test Conditions/Comments3
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
www.DataSheet.net/
Rev. 0 | Page 5 of 28
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
8
6
4
2
0
–2
–4
–6
–8
VDD = 5V
TA = 25°C
–10 REFERENCE = 2.5V
0 10000 20000
30000
40000
CODE
Figure 8. AD5686 INL
50000
60000
10
8
6
4
2
0
–2
–4
–6
–8
VDD = 5V
TA = 25°C
–10 REFERENCE = 2.5V
0 625 1250
1875
2500
CODE
Figure 9. AD5684 INL
3125
3750 4096
www.DataSheet.net/
AD5686/AD5684
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
VDD = 5V
TA = 25°C
–1.0 REFERENCE = 2.5V
0 625 1250
1875
2500
CODE
Figure 11. AD5684 DNL
3125
3750 4096
10
8
6
4
2 INL
0
DNL
–2
–4
–6
–8
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
–40 10
60 110
TEMPERATURE (°C)
Figure 12. INL Error and DNL Error vs. Temperature
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
VDD = 5V
TA = 25°C
–1.0 REFERENCE = 2.5V
0 10000 20000
30000
40000
CODE
Figure 10. AD5686 DNL
50000
60000
10
8
6
4
2
INL
0
DNL
–2
–4
–6
–8
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
Figure 13. INL Error and DNL Error vs. VREF
Rev. 0 | Page 11 of 28
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5686.PDF ] | |
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