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PDF W25Q16CL Data sheet ( Hoja de datos )
| Número de pieza | W25Q16CL | |
| Descripción | 2.5V 16M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W25Q16CL
2.5V 16M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
www.DataSheet.net/
-1-
Publication Release Date: July 08, 2010
Preliminary - Revision A
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
W25Q16CL
1. GENERAL DESCRIPTION
The W25Q16CL (16M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power supply with
current consumption as low as 4mA active and 1µA for power-down.
The W25Q16CL array is organized into 8,192 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16CL
has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q16CL supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 50MHz are supported allowing
equivalent clock rates of 100MHz (50MHz x 2) for Dual I/O and 200MHz (50MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true
XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification with a 64-bit Unique Serial Number.
2. FEATURES
• Family of SpiFlash Memories
– W25Q16CL: 16M-bit / 2M-byte (2,097,152)
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash
– 50MHz Dual SPI / Quad SPI clocks
– 100/200MHz equivalent Dual/Quad SPI
– 25MB/S continuous data transfer rate
– Up to 4X that of ordinary Serial Flash
– More than 100,000 erase/program cycles
– More than 20-year data retention
• Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
• Low Power, Wide Temperature Range
– Single 2.3 to 3.6V supply
–www.DataSheet.net/ 4mA active current, <1µA Power-down (typ.)
– -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Uniform Block Erase (32K and 64K-bytes)
– Program one to 256 bytes
– Erase/Program Suspend & Resume
• Advanced Security & Identification Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Power Supply Lock-Down and OTP protection
– 64-Bit Unique ID for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
• Space Efficient Packaging
– 8-pin SOIC 150(1)/208-mil
– 8-pad WSON 6x5-mm
– 8-pin PDIP 300-mil(1)
– 16-pin SOIC 300-mil(1)
– Contact Winbond for KGD and other options
Note 1. These are special order packages, please contact Winbond for ordering information.
-5-
Publication Release Date: July 08, 2010
Preliminary - Revision A
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
W25Q16CL
10. FUNCTIONAL DESCRIPTION
10.1 SPI OPERATIONS
10.1.1 Standard SPI Instructions
The W25Q16CL is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
10.1.2 Dual SPI Instructions
The W25Q16CL supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast
Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at
two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
www.DataSheet.net/
10.1.3 Quad SPI Instructions
The W25Q16CL supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast
Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)” instructions.
These instructions allow data to be transferred to or from the device four to six times the rate of ordinary
Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random
access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP).
When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP
and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set.
10.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q16CL operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume
where it left off once the bus is available again. The /HOLD function is only available for standard SPI and
Dual SPI operation, not during Quad SPI.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
- 11 -
Publication Release Date: July 08, 2010
Preliminary - Revision A
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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