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PDF LTM9010-14 Data sheet ( Hoja de datos )
| Número de pieza | LTM9010-14 | |
| Descripción | 125Msps/105Msps/ 80Msps Low Power Octal ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTM9010-14 (archivo pdf) en la parte inferior de esta página. Total 36 Páginas | ||
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Electrical Specifications Subject to Change
LTM9011-14/
LTM9010-14/LTM9009-14
14-Bit, 125Msps/105Msps/
80Msps Low Power Octal ADCs
Features
Description
n 8-Channel Simultaneous Sampling ADC
n 73.1dB SNR
n 88dB SFDR
n Low Power: 140mW/113mW/94mW per Channel
n Single 1.8V Supply
n Serial LVDS Outputs: 1 or 2 Bits per Channel
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full Power Bandwidth S/H
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Internal Bypass Capacitance, No External
Components
n 140-Pin (9mm × 11.25mm) BGA Package
Applications
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
AC performance includes 73.1dB SNR and 88dB spurious
free dynamic range (SFDR). Low power consumption per
channel reduces heat in high channel count applications.
Integrated bypass capacitance and flow-through pinout
reduces overall board space requirements.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.2LSBRMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode).
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOSwww.DataSheet.net/ inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
CHANNEL 1
ANALOG
INPUT
S/H
1.8V
VDD
14-BIT
ADC CORE
1.8V
OVDD
CHANNEL 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
DATA
SERIALIZER
CHANNEL 8
ANALOG
INPUT
S/H
14-BIT
ADC CORE
ENCODE
INPUT
PLL
GND OGND
OUT1A
OUT1B
OUT2A
OUT2B
OUT8A
OUT8B
DATA
CLOCK
OUT
FRAME
SERIALIZED
LVDS
OUTPUTS
9009101114 TA01
LTM9011-14, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
9009101114 TA01b
9009101114p
1
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
LTM9011-14/
LTM9010-14/LTM9009-14
D igital Inputs And Outputs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID Differential Input Voltage
VICM Common Mode Input Voltage
(Note 8)
Internally Set
Externally Set (Note 8)
l 0.2
1.2
l 1.1
1.6
V
V
V
VIN Input Voltage Range
RIN Input Resistance
CIN Input Capacitance
Single-Ended Encode Mode (ENC– Tied to GND)
ENC+, ENC– to GND
(See Figure 10)
l 0.2
3.6 V
10 kΩ
3.5 pF
VIH High Level Input Voltage
VDD = 1.8V
l 1.2
V
VIL Low Level Input Voltage
VDD = 1.8V
l
0.6 V
VIN Input Voltage Range
ENC+ to GND
l0
3.6 V
RIN Input Resistance
(See Figure 11)
30 kΩ
CIN Input Capacitance
3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage
VDD = 1.8V
l 1.3
V
VIL Low Level Input Voltage
VDD = 1.8V
l
0.6 V
IIN Input Current
VIN = 0V to 3.6V
l –10
10 µA
CIN Input Capacitance
3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
www.DataSheet.net/
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V
200 Ω
IOH Logic High Output Leakage Current
SDO = 0V to 3.6V
l –10
10 µA
COUT Output Capacitance
3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
l 247
350
454
mV
100Ω Differential Load, 1.75mA Mode
l 125
175
250
mV
VOS Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 1.125
l 1.125
1.250
1.250
1.375
1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100 Ω
9009101114p
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
timing DIAGRAMS
LTM9011-14/
LTM9010-14/LTM9009-14
SPI Port Timing (Readback Mode)
tS
CS
tDS tDH tSCK
tH
SCK
tDO
SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX
SDO
HIGH IMPEDANCE
D7 D6 D5 D4 D3 D2 D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
www.DataSheet.net/
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
9009101114 TD08
9009101114p
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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| PDF Descargar | [ Datasheet LTM9010-14.PDF ] | |
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