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PDF 14553B Data sheet ( Hoja de datos )
| Número de pieza | 14553B | |
| Descripción | MC14553B | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 14553B (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MC14553B
3−Digit BCD Counter
The MC14553B 3−digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on−chip oscillator provides the low−frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
Features
• TTL Compatible Outputs
• On−Chip Oscillator
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock
• Output Latches
• Master Reset
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
www.DataSheet.net/
Unit
DC Supply Voltage Range
VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, −0.5 to VDD V
Vout + 0.5
Input Current (DC or Transient) per Pin
Iin
±10 mA
Output Current (DC or Transient) per Pin
Iout
+20 mA
Power Dissipation, per Package (Note 1)
PD
500 mW
Ambient Temperature Range
TA −55 to +125 °C
Storage Temperature Range
Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering)
TL
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 7
1
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 16
P SUFFIX
CASE 648
1
MC14553BCP
AWLYYWWG
1
16
SO−16W
DW SUFFIX
1 CASE 751G
MC14553B
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
43
CIA CIB Q0
9
12 CLOCK
Q1 7
10 LE
11 DIS
13 MR
Q2 6
Q3 5
O.F. 14
DS1 2
DS2 1
DS3 15
VDD = PIN 16
VSS = PIN 8
Figure 1. Block Diagram
ORDERING INFORMATION
Device
MC14553BCP
MC14553BCPG
MC14553BDW
Package
PDIP−16
PDIP−16
(Pb−Free)
SOIC−16
Shipping
25 Units / Rail
25 Units / Rail
47 Units / Rail
Publication Order Number:
MC14553B/D
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
MC14553B
OPERATING CHARACTERISTICS
The MC14553B three−digit counter, shown in Figure 4,
consists of three negative edge−triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits
storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time
division multiplexed, providing one BCD number or digit at
a time. Digit select outputs (active low) are provided for
display control. All outputs are TTL compatible.
An on−chip oscillator provides the low frequency
scanning clock which drives the multiplexer output selector.
The frequency of the oscillator can be controlled externally
by a capacitor between pins 3 and 4, or it can be overridden
and driven with an external clock at pin 4. Multiple devices
can be cascaded using the overflow output, which provides
one pulse for every 1000 counts.
LATCH ENABLE
10
CLOCK
12
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three−digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue
operating on input pulses with very slow rise times.
Information present in the counters when the latch input
goes high, will be stored in the latches and will be retained
while the latch input is high, independent of other inputs.
Information can be recovered from the latches after the
counters have been reset if Latch Enable remains high
during the entire reset cycle.
C1A
ROSCSICLLAANTOR
4
3
C1B
R SCANNER
PULSE
C1 GENERATOR
PULSE
SHAPER
11
DISABLE
(ACTIVE
HIGH)
Q0
C Q1
Q2
R ÷ 10 Q3
UNITS
C
Q0
Q1
Q2
R ÷ 10 Q3
TENS
QUAD
LATCH
QUAD
LATCH
www.DataSheet.net/
MULTIPLEXER
9
Q0
7
Q1
BCD
OUTPUTS
(ACTIVE
HIGH)
6
Q2
Q0
C Q1
Q2
R ÷ 10 Q3
HUNDREDS
QUAD
LATCH
5
Q3
13
MR
(ACTIVE HIGH)
14
OVERFLOW
2 1 15
DS1 DS2 DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
Figure 4. Expanded Block Diagram
http://onsemi.com
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 14553B.PDF ] | |
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