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PDF HMCAD1041-40 Data sheet ( Hoja de datos )
| Número de pieza | HMCAD1041-40 | |
| Descripción | Single 10-Bit 20/40 MSPS A/D Converter | |
| Fabricantes | Hittite | |
| Logotipo |  |
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v01.0411
Features
• 10-bit resolution
• 20/40 MSPS maximum sampling rate
• Ultra-Low Power Dissipation: 15/25 mW
• 61.6 dB SNR @ 8 MHz FIN
• Internal reference circuitry
• 1.8 V core supply voltage
• 1.7 - 3.6 V I/O supply voltage
• Parallel CMOS output
• 6 x 6 mm 40-Pin QFN (LP6HE) Package
0 Typical Applications
• Medical Imaging
• Portable Test Equipment
• Digital Oscilloscopes
• IF Communication
Functional Diagram
HMCAD1041-40
Single 10-Bit 20/40 MSPS
A/D Converter
General Description
The HMCAD1041-40 is a high performance ultra
low power analog-to-digital converter (ADC). The
ADC employs internal reference circuitry, a CMOS
control interface, CMOS output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
Two idle modes with fast startup times exist. The entire
chip can either be put in Standby Mode or Power
Down mode. The two modes are optimized to allow
the user to select the mode resulting in the lowest
possible energy consumption during idle mode and
startup.
The HMCAD1041-40 has a highly linear THA optim-
ized for frequencies up to Nyquist. The differential
clock interface is optimized for low jitter clock sources
and supports LVDS, LVPECL, sine wave and CMOS
clock inputs.
Pin compatible with HMCAD1041-80, HMCAD1051-40
and HMCAD1051-80.
www.DataSheet.net/
0-1
Figure 1. Functional Block Diagram
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
HMCAD1041-40
v01.0411
Single 10-Bit 20/40 MSPS A/D Converter
0
Digital and Timing Specifications
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, Conversion Rate: Max specified, 50% clock duty cycle, -1dBFS input signal, 5 pF capacitive
load on data outputs, unless otherwise noted
Parameter
Condition
Min
Typ
Max
Unit
Clock Inputs
Duty Cycle
20 80 % high
Compliance
CMOS, LVDS, LVPECL, Sine Wave
Input range
Differential input swing
0.4
Vpp
Input range
Differential input swing, sine wave clock input
1.6
Vpp
Input common mode
voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input capacitance
Differential
2 pF
Timing
TPD Start up time from Power Down Mode to Active Mode
TSLP Start up time from Sleep Mode to Active Mode
TOVR Out of range recovery time
900
clock
cycles
20
clock
cylcles
1
clock
cycles
TAP
Єrms
Aperture Delay
Aperture jitter
0.8
< 0.5
ns
ps
TLAT
Pipeline Delay
www.DataSheet.net/
12
TD
TDC
Logic Inputs
Output delay (see timing diagram). 5pF load on output bits
Output delay relative to CK_EXT (see timing diagram)
3
1
10
6
VHI
VHI
VLI
VLI
IHI
ILI
CI
Logic Outputs
High Level Input Voltage. VOVDD ≥ 3.0V
High Level Input Voltage. VOVDD = 1.7V – 3.0V
Low Level Input Voltage. VOVDD ≥ 3.0V
Low Level Input Voltage. VOVDD = 1.7V – 3.0V
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
2
0.8 ·VOVDD
0
0.8
0 0.2 ·VOVDD
±10
±10
3
VHO
High Level Output Voltage
VOVDD -0.1
VLO Low Level Output Voltage
0.1
CL
Max capacitive load. Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOCVDD
5
CL Max capacitive load. Post-driver supply voltage above 2.25V (1)
10
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible
to keep dynamic currents and resulting switching noise at a minimum
clock
cycles
ns
ns
V
V
V
V
µA
µA
pF
V
V
pF
pF
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
HMCAD1041-40
v01.0411
Single 10-Bit 20/40 MSPS A/D Converter
If the clock is generated by other circuitry, it should
The HMCAD1041-40 employs digital offset correc-
be re-timed with a low jitter master clock as the last
tion. This means that the output code will be 4096 with
operation before it is applied to the ADC clock input.
shorted inputs. However, small mismatches in para-
Digital Outputs
Digital output data are presented on parallel CMOS
form. The voltage on the OVDD pin set the levels of the
CMOS outputs. The output drivers are dimensioned to
drive a wide range of loads for OVDD above 2.25V,
but it is recommended to minimize the load to ensure
as low transient switching currents and resulting noise
as possible. In applications with a large fanout or large
sitics at the input can cause this to alter slightly. The
offset correction also results in possible loss of codes
at the edges of the full scale range. With no offset
correction, the ADC would clip in one end before the
other, in practice resulting in code loss at the oppo-
site end. With the output being centered digitally, the
output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags
are set, the code is forced to all ones for overrange
capacitive loads, it is recommended to add external
and all zeros for underrange.
buffers located close to the ADC chip.
Data Format Selection
0 The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT
always should be lower than the load on data outputs
to ensure sufficient timing margins.
The output data are presented on offset binary form
when DFRMT is low (connect to OVSS). Setting
DFRMT high (connect to OVDD) results in 2’s comple-
ment output format. Details are shown in table 3.
The digital outputs can be set in tristate mode by set-
ting the OE_N signal high.
Table 3: Data Format Description for 2Vpp Full Scale Range
Differential Input Voltage (IP - IN)
Output Data: D_9 : D_0
(DFRMT = 0, Offset Binary)
1.0 V
11 1111 1111www.DataSheet.net/
+0.24mV
10 0000 0000
-0.24mV
01 1111 1111
-1.0V
00 0000 0000
Output Data: D_9 : D_0
(DFRMT = 1, 2’s Complement)
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
Reference Voltages
The reference voltages are internally generated and
buffered based on a bandgap voltage reference. No
external decoupling is necessary, and the reference
voltages are not available externally. This simplifies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
Operational Modes
The operational modes are controlled with the PD_N
and SLP_N pins. If PD_N is set low, all other control
pins are overridden and the chip is set in Power Down
mode. In this mode all circuitry is completely turned off
and the internal clock is disabled. Hence, only leak-
age current contributes to the Power Down Dissipa-
tion. The startup time from this mode is longer than
for Sleep Mode as all references need to settle to their
final values before normal operation can resume.
The SLP_N signal can be used to set the full chip in
Sleep Mode. In this mode internal clocking is disabled,
but some low bandwidth circuitry is kept on to allow for
a short startup time. However, Sleep Mode represents
a significant reduction in supply current, and it can be
used to save power even for short idle periods.
The input clock should be kept running in all idle
modes. However, even lower power dissipation is pos-
sible in Power Down mode if the input clock is stopped.
In this case it is important to start the input clock prior
to enabling active mode.
Startup Initialization
The HMCAD1041-40 must be reset prior to normal
operation. This is required every time the power
supply voltage has been switched off. A reset is per-
formed by applying Power Down mode. Wait until a
stable supply voltage has been reached, and pull the
PD_N pin for the duration of at least one clock cycle.
The input clock must be running continuously during
this Power Down period and until active operation
is reached. Alternatively the PD pin can be kept low
during power-up, and then be set high when the power
supply voltage is stable.
0 - 11
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HMCAD1041-40.PDF ] | |
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