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PDF HMCAD1040-80 Data sheet ( Hoja de datos )
| Número de pieza | HMCAD1040-80 | |
| Descripción | Dual 10-Bit 65/80 MSPS A/D Converter | |
| Fabricantes | Hittite | |
| Logotipo |  |
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v01.0411
Features
• 10-bit Resolution
• 65/80 MSPS Maximum Sampling Rate
• Ultra-Low Power Dissipation: 65/78 mW
• 61.6 dB SNR @ 8 MHz
• Internal Reference Circuitry
• 1.8 V Core Supply Voltage
• 1.7 – 3.6 V I/O Supply Voltage
• Parallel CMOS Output
0 • 9 x 9 mm, 64-Pin QFN (LP9E) Package
• Dual Channel
Typical Applications
• Medical Imaging
• Portable Test Equipment
• Digital Oscilloscopes
• IF Communication
Functional Diagram
HMCAD1040-80
Dual 10-Bit 65/80 MSPS
A/D Converter
General Description
The HMCAD1040-80 is a high performance low
power dual analog-to-digital converter (ADC). The
ADC employs internal reference circuitry, a CMOS
control interface, CMOS output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
Several idle modes with fast startup times exist. Each
channel can be independently powered down and
the entire chip can either be put in Standby Mode or
Power Down mode. The different modes are optimized
to allow the user to select the mode resulting in
the lowest possible energy consumption during idle
mode and startup.
The HMCAD1040-80 has a highly linear THA optimi-
zed for frequencies up to Nyquist. The differential
clock interface is optimized for low jitter clock sources
and supports LVDS, LVPECL, sine wave and CMOS
clock inputs.
Pin compatible with HMCAD1040-40, HMCAD1050-40
and HMCAD1050-80.www.DataSheet.net/
0-1
Figure 1.Functional Block Diagram
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
0
v01.0411
HMCAD1040-80
Dual 10-Bit 65/80 MSPS
A/D Converter
Digital & Timing Specifications
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, Conversion Rate: Max specified, 50% clock duty cycle, -1dBFS input signal,
5 pF capacitive load on data outputs, unless otherwise noted
Parameter
Condition
Min
Typ
Max
Unit
Clock Inputs
Duty Cycle
20 80 % high
Compliance
CMOS, LVDS, LVPECL, Sine Wave
Input range
Differential input swing
0.4
Vpp
Input range
Differential input swing, sine wave clock input
1.6
Vpp
Input common
mode voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input capacitance
Differential
2 pF
Timing
TPD
TSLP
TOVR
TAP
Єrms
Start up time from Power Down Mode to Active Mode
Start up time from Sleep Mode to Active Mode
Out of range recovery time
Aperture Delay
Aperture jitter
1
0.8
< 0.5
900 clock cycles
20 clock cycles
clock cycles
ns
ps
TLAT
TD
TDC
Logic Inputs
Pipeline Delay
Output delay (see timing diagram). 5pF load on output bits
Output delay relative to CK_EXT (see timing diagram)
www.DataSheet.net/
3
1
12 clock cycles
10 ns
6 ns
VHI
VHI
VLI
VLI
IHI
ILI
CI
Logic Outputs
High Level Input Voltage. VOVDD ≥ 3.0V
High Level Input Voltage. VOVDD = 1.7V – 3.0V
Low Level Input Voltage. VOVDD ≥ 3.0V
Low Level Input Voltage. VOVDD = 1.7V – 3.0V
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
2V
0.8 ·VOVDD
0
V
0.8 V
0
0.2 ·VOVDD
V
±10 µA
±10 µA
3 pF
VHO
High Level Output Voltage
VOVDD -0.1
V
VLO Low Level Output Voltage
0.1 V
CL
Max capacitive load. Post-driver supply voltage equal to
pre-driver supply voltage VOVDD = VOCVDD
5 pF
CL
Max capacitive load. Post-driver supply voltage above 2.25V [1]
10
pF
[1] The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep
dynamic currents and resulting switching noise at a minimum
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
v01.0411
HMCAD1040-80
Dual 10-Bit 65/80 MSPS
A/D Converter
0
0 - 11
Figure 7 shows AC-coupling using capacitors.
Resistors from the CM_EXT output, RCM, should be
used to bias the differential input signals to the correct
voltage. The series capacitor, CI, form the high-
pass pole with these resistors, and the values must
therefore be determined based on the requirement to
the high-pass cut-off frequency.
Figure 7. AC coupled input
Figure 8. Alternative input network
Note that startup time from Sleep Mode and Power
Down Mode will be affected by this filter as the time
required to charge the series capacitors is dependent
on the filter cut-off frequency.
If the input signal has a long traveling distance, and
the kick-backs from the ADC not are effectively
terminated at the signal source, the input network of
figure 8 can be used. The configuration in figure 8 is
designed to attenuate the kickback from the ADC and
to provide an input impedance that looks as resistive
as possible for frequencies below Nyquist. Values
of the series inductor will however depend on board
design and conversion rate. In some instances a
shunt capacitor in parallel with the termination resistor
(e.g. 33 pF) may improve ADC performance further.
This capacitor attenuates the ADC kick-back even
more, and minimizes the kicks traveling towards the
source. However, the impedance match seen into the
transformer becomes worse.
Clock Input and Jitter considerations
Typically high-speed ADCs use both clock edges to
generate internal timing signals. In the HMCAD1040-80
only the rising edge of the clock is used. Hence,
input clock duty cycles between 20% and 80% are
acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally. Hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine
wave can be connected directly to the input pins.
For CMOS inputs, the CKN pin should be connected
to ground, and the CMOS clock signal should be
connected to CKP. For differential sine wave clock, the
input amplitude must be at least ± 800 mVpp.
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to
SNR from clock jitter with a full scale signal at a given
frequency is shown in equation 1,
SNRjitter = 20 · log (2 · π · ƒIN · єt) (1)
where fIN is the signal frequency, and εt is the total
rms jitter measured in seconds. The rms jitter is the
total of all jitter sources including the clock generation
circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the clock
jitter.www.DataSheet.net/ This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution
is well controlled. It might be advantageous to use
analog power and ground planes to ensure low noise
on the supplies to all circuitry in the clock distribution.
It is of utmost importance to avoid crosstalk between
the ADC output bits and the clock and between the
analog input signal and the clock since such crosstalk
often results in harmonic distortion.
The jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LVDS or LVPECL clock
with fast edges. CMOS and sine wave clock inputs will
result in slightly degraded jitter performance.
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Digital Outputs
Digital output data are presented in parallel CMOS
form. The voltage on the OVDD pin sets the levels of the
CMOS outputs. The output drivers are dimensioned to
drive a wide range of loads for OVDD above 2.25V,
but it is recommended to minimize the load to ensure
as low transient switching currents and resulting noise
as possible. In applications with a large fanout or large
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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| PDF Descargar | [ Datasheet HMCAD1040-80.PDF ] | |
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