PDF X25170 Data sheet ( Hoja de datos )

Número de pieza	X25170
Descripción	SPI Serial E2PROM
Fabricantes	ICMIC
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No Preview Available ! This X25170 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmicTM IC MICROSYSTEMS 16K X25170 2K x 8 Bit SPI Serial E 2PROM with Block Lock ™ Protection FEATURES •5MHz Clock Rate •SPI Modes (0,0 & 1,1) •2K X 8 Bits —32 byte page mode •Low Power CMOS —<1µA standby current —<5mA active current •2.5V To 5.5V Power Supply •Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM array •Built-In Inadvertent Write Protection —Power-up/power-down protection circuitry —Write enable latch —Write protect pin •Self-Timed Write Cycle —5ms write cycle time (typical) •High Reliability —Endurance: 100,000 cycles —Data retention: 100 Years —ESD protection: 2000V on all pins •8-Lead PDlP Package •8-Lead SOIC Package •14-Lead TSSOP Package DESCRIPTION The X25170 is a CMOS 16384-bit serial E2PROM, internally organized as 2K x 8. The X25170 features a Serial Peripheral Interface (SPI) and software protocol, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25170 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25170 will ignore transitions on its inputs, thus allowing the host to service higher prior- ity interrupts. The WP input can be used as a hardwire input to the X25170 (disabling all write attempts to the status register), thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25170 utilizes Xicor’s proprietary Direct Write ™ cell, providing a minimum endurance of 100,000 cycles and a www.DataSheet.co.kr minimum data retention of 100 years. BLOCK DIAGRAM Status Register SO SI SCK CS HOLD Command Decode and Control Logic Write Protect Logic Write Control and WP Timing Logic Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 2000 Patents Pending 9900-5004.9 5/26/00 EP X Decode Logic 16 2K Byte Array 16 X 256 16 16 X 256 32 32 X 256 32 8 Y Decode Data Register Characteristics subject to change without notice. 1 of 15 Datasheet pdf - http://www.DataSheet4U.net/ 1 page X25170 Figure 1. Read E2PROM Array Operation Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 Instruction SI 16 Bit Address 15 14 13 3 210 High Impedance SO Figure 2. Read Status Register Operation Sequence CS Data Out 7 65432 10 MSB SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Instruction www.DataSheet.co.kr High Impedance SO Data Out 76543210 MSB Write Sequence Prior to any attempt to write data into the X25170, the “write enable” latch must ﬁrst be set by issuing the WREN instruction (See Figure 3). CS is ﬁrst taken LOW, then the WREN instruction is clocked into the X25170. After all eight bits of the instruction are trans- mitted, CS must then be taken HIGH. If the user con- tinues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25170. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the ﬁrst address of the page and overwrite any data that may have been written. Characteristics subject to change without notice. 5 of 15 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page X25170 Hold Timing CS SCK SO SI HOLD SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady May change from LOW May change from HIGH to LOW Don’t Care: Changes Allowed N/A Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance tHD tHZ tCD tCD tHD tLZ www.DataSheet.co.kr Characteristics subject to change without notice. 11 of 15 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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