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PDF NCV8851 Data sheet ( Hoja de datos )
| Número de pieza | NCV8851 | |
| Descripción | Automotive Grade Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV8851
Automotive Grade
Synchronous Buck
Controller
The NCV8851 is an adjustable output, synchronous buck controller,
which drives dual N−channel MOSFETs, ideal for high power
applications. Average current mode control is employed for very fast
transient response and tight regulation over wide input voltage and
output load ranges. The IC incorporates an internal fixed 6.0 V
low−dropout linear regulator (LDO), which supplies charge to the
switch mode power supply’s (SMPS) bottom gate driver, limiting the
power lost to excess gate drive. The IC is designed for operation over a
wide input voltage range (4.5 V to 20 V) and is capable of 10 to 1
voltage conversion at 500 kHz.
Additional controller features include undervoltage lockout,
internal soft start, low quiescent current sleep mode, programmable
frequency, SYNC function, average current limiting, cycle−by−cycle
overcurrent protection and thermal shutdown.
Features
• Average Current Mode Control
• 0.8 V ±2% Reference Voltage
• Input Voltage Range of 4.5 V to 20 V
• 6.0 V Low−dropout Linear Regulator (LDO)
• Input UVLO (Undervoltage Lockout)
• Internal Soft−start
• 1.0 mA Maximum Quiescent Current in Sleep Mode
• Adaptive Non−overlap Circuitry
• 150 ns Minimum High−side Gate Off−time
• Programmable Fixed Frequency – 170 kHz to 500 kHz
• External Clock Synchronization up to 600 kHz
• Average Current Limiting (ACL)
• Cycle−by−Cycle Overcurrent Protection (OCP)
• Thermal Shutdown (TSD)
www.DataSheet.co.kr
Applications
• Automotive Systems Requiring High Current
• Pre−regulated Supply for Low−voltage SMPSs and LDOs
http://onsemi.com
TSSOP−20
SUFFIX DB
CASE 948E
MARKING DIAGRAM
NCV
8851
ALYWG
G
NCV8851 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NCV8851DBG
Package
TSSOP−20
(Pb−Free)
Shipping†
75 Units/Rail
NCV8851DBR2G TSSOP−20 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
April, 2010 − Rev. 2
1
Publication Order Number:
NCV8851/D
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
NCV8851
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 4.5 V < VIN < 20 V, 4.5 V < BST < 46 V, ROSC = 51.1 kW, unless otherwise specified)
Characteristic
Conditions
Min
Typ
CURRENT ERROR AMPLIFIER
DC Gain
Guaranteed by Design
70 73
Gain−Bandwidth Product
Guaranteed by Design
8.0 10
Charge Currents
FB Bias Current
Source, CCOMP = 1.75 V
Sink, CCOMP = 1.75 V
Guaranteed by Design
24
1.3 3
− 0.1
Clamping Voltage
2.7 3.5
CURRENT LIMIT
Average Current Limit Threshold
1.2 V ≤ CSN ≤ 10.0 V
80 100
Cycle−by−Cycle Current Limit
Threshold Voltage
115 165
Cycle−by−Cycle Current Limit
Response Time
Guaranteed by Design
− 200
Cycle−by−Cycle and Average Cur-
rent Limit Threshold Difference
20 −
SYNC
SYNC Frequency Range
SYNC Pin Bias Current
SYNC Threshold Voltage
VSYNC = 0 V
VSYNC = 5.0 V
Logic Low
Logic High
FSW
−
−
−
2.0
−
0.1
10
−
−
6.0 V LDO
Output Voltage
Dropout Voltage
Current Limit
IOUT = 20 mA
www.DataSheet.co.kr
IOUT = 20 mA
5.8 6.0
−−
30 75
GATE DRIVERS
GH Sink Current
GH Source Current
VGH = 2 V, VIN_IC = 6 V, Guaranteed by Design
VGH = 4 V, VIN_IC = 6 V, Guaranteed by Design
−
−
1.5
1.5
GL Sink Current
GL Source Current
VIN_IC = 6 V
VGL = 1.0 V
Guaranteed by Design
− 1.5
− 1.5
GH to GL Delay
GL to GH Delay
SOFT START
VIN = 13.2 V
VIN = 13.2 V
− 40
− 40
Time
ENABLE (EN)
FSW = 170 kHz
− 14
Input Threshold
Logic Low
Logic High
−−
2.0 −
Input Current
EN = 2.0 V
− 3.0
Max Unit
− dB
− MHz
− mA
− mA
1.0 mA
−V
125 mV
215 mV
− ns
− mV
600 kHz
0.2 mA
20
0.8 V
−
6.2 V
200 mV
120 mA
−A
−A
−A
−A
70 ns
70 ns
− ms
0.8 V
−
10 mA
http://onsemi.com
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
NCV8851
Careful selection and layout of external components is
required to realize the full benefit of the onboard drivers.
The capacitors between VIN and GND and between BST
and VSW must be placed as close as possible to the IC. The
current paths for the GH and GL connections must be
optimized, minimizing parasitic resistance and inductance.
Current Limiting and Overcurrent Protection
The NCV8851 contains average current limiting (ACL)
and cycle−by−cycle overcurrent protection (OCP) to protect
the power switches, inductor, current sense resistor and
other external components. The current through the inductor
is continuously sensed using the CSP and CSN pins. A sense
resistor is placed between these pins to translate the output
current to a proportional voltage. This voltage is compared
to a fixed internal voltage threshold.
When the differential voltage exceeds the ACL threshold,
the PWM pulse is terminated for this cycle, limiting the
current through the inductor. In steady−state operation,
decreasing the load resistance while in ACL will cause the
duty cycle and VOUT to decrease proportionally without
skipping pulses or jitter.
There is also a fast OCP path which is tripped when the
differential voltage exceeds the OCP threshold, which is
above the ACL threshold. This causes the PWM pulse to be
terminated very quickly and disables the part from switching
back on until the current through the inductor has dropped
below the OCP threshold. Once the inductor current is below
the OCP threshold, the part will begin switching again and
the current will be limited by ACL, until the inductor current
drops below the ACL threshold.
An advantage of this current limiting scheme is that the
NCV8851 will limit large transient currents yet resume
normal operation on the following cycle. Additionally, the
current will not run away, nor will the part latch off in case
of a short, which is typical of other current limiting schemes
employing high−side current sensing.
SYNC Feature
An external clock signal can synchronize the NCV8851 to
a higher frequency. The rising edge of the SYNC pulse turns
on the power switch to start a new switching cycle, as shown
in Figure 24. There is a 0.5 ms delay between the rising edge
of the SYNC pulse and rising edge of the VSW pin voltage.
The SYNC threshold is TTL logic compatible, and duty
cycle of the SYNC pulses can vary from 10% to 90%. The
SYNC frequency must be higher than the internal oscillator
frequency set by ROSC.
www.DataSheet.co.kr
Figure 24. Synchronization from 170 kHz to an external 600 kHz signal
Snubber
A snubber consisting of a 4300 pF ceramic capacitor and
a 1 W reistor from switch node to ground is required to
decrease noise susceptibility. The resistor should be rated for
0.5 W of power dissipation for switching frequencies below
280 kHz and 1 W of power dissipation for switching
frequencies above 280 kHz. The snubber should be placed
close to the switch node pin.
http://onsemi.com
11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NCV8851.PDF ] | |
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