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Número de pieza | A024CN02_V1 | |
Descripción | COLOR TFT-LCD MODULE | |
Fabricantes | AUO | |
Logotipo | ||
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Date
: 2 0 04 . 11 . 29
Product Specification
2.36〞COLOR TFT-LCD MODULE
MODEL NAME: A0 24CN0 2 V1
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< ◆ > Preliminary Specification
< > Final Specification
Note: The content of this
specification is subject to
change.
© 2004 AU Optronics
All Rights Reserved,
Do Not Copy.
Datasheet pdf - http:/
1 page B. Electrical specifications
1.Pin assignment
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Pin no
1
2
3
4
5
Symbol
VCOM
Vgoff_H
Vgoff_L
C4P
C4M
I/O Description
I Common electrode driving voltage
PO Negative high power supply for gate driver output: -12.5V+VCAC
PO Negative low power supply for gate driver output: -12.5V
C Pins to connect capacitance for power circuitry
C Pins to connect capacitance for power circuitry
Remark
6 VGH PO Positive power supply for gate driver output: +12.5V
7 FRP O Frame polarity output for VCOM
8 VCAC C Define the amplitude of the VCOM swing
9
Vint3
P Intermediate voltage for charge Pump
10 C3P C Pins to connect capacitance for power circuitry
11
C3M
C Pins to connect capacitance for power circuitry
12
Vint2
P Intermediate voltage for charge Pump
13 C2P C Pins to connect capacitance for power circuitry
14
C2M
C Pins to connect capacitance forwww.DataSheet.co.kr power circuitry
15
Vint1
P Intermediate voltage for charge Pump
16 C1P C Pins to connect capacitance for power circuitry
17 C1M C Pins to connect capacitance for power circuitry
18 PGND P Charge Pump Power GND
19 PVDD P Charge Pump Power VDD
20 DRV PO Gate signal for the power transistor of the boost converter
21 LED Anode I For Led Anode voltage
22
GND
P Digital GND
23 FB P Main boost regulator feedback input
24 AVDD P Analog power supply
25
GND
P Digital GND
26
VCC
P Digital power supply
27 CS I Serial communication chip select
28
SDA
I Serial communication data input
29 SCL I Serial communication clock input
30 HSYNC I Horizontal sync input
31 VSYNC I Vertical sync input
32
DCLK
I Clock Input:
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/
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R0 SHDB
I DC-DC converter shutdown signal (active low)
SHDB=”L”: DC-DC converter is off. Default setting.
SHDB=”H”: DC-DC converter is on.
R0 SHCB
I Charge pump shutdown signal (active low).
SHDB=”L”: Charge pump is off.
SHDB=”H”: Charge pump is on. Default setting.
R2 U/D
I Up/down scan control of gate driver.
U/D=”L”: Scan up: First line=G240èG239è…èG2èLast line=G1.
U/D=”H”: Scan down: First line=G1èG2è…èG239èLast line=G240.
Default setting.
R2 SHL
I Select left or right shift.
SHL=”L”: Shift left: First data=S480èS479è…èS2èLast data=S1.
SHL=”H”: Shift right: First data=S1èS2è…èS479èLast data=S480.
Default setting.
R3 PAL
I NTSC/PAL selection signal
PAL=”L”: Input data format is NTSC (240 active line). Default setting.
PAL=”H”: Input data format is PAL.
R3 PALM
R3 SEL [2…0]
I PAL selection signal
PALM=”L”: Input data format is PAL 1/6,8(280 active line). Default setting.
PALM=”H”: Input data format is PAL 1/6(288 active line).
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Only available when PAL=H.
I Select input data format.
I VCAC voltage selection
R6 VSCL [2...0]
VCSL
010
011
100
101
110
111
000
001
VCAC[V]
5
5.2
5.4
5.6
5.8
6
6.2
6.4
I Luminance data averaging
R7 AVGY
AVGY=”L”: Only odd Y sample used for YUV conversion
AVGY=”H”: Use odd and even Y sample for YUV conversion. Default setting.
I Delta mode data alignment
R7 DMDA
DMDA=”L”: Data alignment does not take care of Delta pixels arrangement.
DMDA=”H”: Data arrangement takes of the Delta pixels arrangement. Default setting.
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/
11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet A024CN02_V1.PDF ] |
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