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PDF ADN4690E Data sheet ( Hoja de datos )
| Número de pieza | ADN4690E | |
| Descripción | (ADN4690E - ADN4695E) High Speed M-LVDS Transceivers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
3.3 V, 100 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
ADN4690E/ADN4692E/ADN4694E/ADN4695E
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 100 Mbps (50 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV
Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4690E/ADN4694E) and 14-lead
(ADN4692E/ADN4695E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
GENERAL DESCRIPTION
The ADN4690E/ADN4692E/ADN4694E/ADN4695E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up
to 100 Mbps (50 MHz). Slew rate control is implemented on the
driver outputs. The receivers detect the bus state with a differential
input of as little as 50 mV over a common-mode voltage range of
−1 V to +3.4 V. ESD protection of up to ±15 kV is implemented
on the bus pins. The parts adhere to the TIA/EIA-899 standard for
M-LVDS and complement TIA/EIA-644 LVDS devices with
additional multipoint capabilities.
The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4694E/ADN4695E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the
inputs are open (open-circuit fail-safe).
FUNCTIONAL BLOCK DIAGRAMS
VCC
ADN4690E/
ADN4694E
RO R
RE A
B
DE
DI D
GND
Figure 1.
VCC
ADN4692E/
ADN4695E
RO R
A
B
RE
DE
DI D
Z
Y
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GND
Figure 2.
The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4690E/ADN4694E) or as full-duplex in a 14-lead
SOIC package (the ADN4692E/ADN4695E). A selection table
for the ADN469xE parts is shown in Table 1.
Table 1. ADN469xE Selection Table
Part No. Receiver Data Rate
ADN4690E Type 1
100 Mbps
ADN4691E Type 1
200 Mbps
ADN4692E Type 1
100 Mbps
ADN4693E Type 1
200 Mbps
ADN4694E Type 2
100 Mbps
ADN4695E Type 2
100 Mbps
ADN4696E Type 2
200 Mbps
ADN4697E Type 2
200 Mbps
SOIC
8-lead
8-lead
14-lead
14-lead
8-lead
14-lead
8-lead
14-lead
Duplex
Half
Half
Full
Full
Half
Full
Half
Full
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages
VA (V)
VB (V)
2.4 0
0 2.4
3.475
3.325
3.425
3.375
−0.925
−1.075
−0.975
−1.025
Input Voltage, Differential
VID (V)
2.4
−2.4
0.15
0.05
0.15
0.05
Input Voltage, Common Mode
VIC (V)
1.2
1.2
3.4
3.4
−1
−1
Receiver Output
RO
H
L
H
L
H
L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol Min Typ Max
DRIVER
Maximum Data Rate
100
Propagation Delay
tPLH, tPHL
2
2.5 3.5
Differential Output Rise/Fall Time
tR, tF 2 2.6 3.2
Pulse Skew |tPHL − tPLH|
tSK 30 150
Part-to-Part Skew
tSK(PP)
0.9
Period Jitter, rms (One Standard Deviation)2 tJ(PER)
23
Peak-to-Peak Jitter2, 4
tJ(PP)
150
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
RECEIVER
Propagation Delay
Rise/Fall Time
Pulse Skew |tRPHL – tRPLH|
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Part-to-Part Skew6
Period Jitter, rms (One Standard Deviation)2
Peak-to-Peak Jitter2, 4
tPHZ
tPLZ
tPZH
tPZL
tRPLH, tRPHL
tR, tF
tSK
tSK
tSK(PP)
tJ(PER)
2
1
4
4
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4
4
100
300
4
7
7
7
7
6
2.3
300
500
1
7
Type 1 Receiver (ADN4690E, ADN4692E)
Type 2 Receiver (ADN4694E, ADN4695E)
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
tJ(PP)
tJ(PP)
tRPHZ
tRPLZ
tRPZH
tRPZL
200 700
225 800
6 10
6 10
10 15
10 15
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
4 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
5 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
6 HP4194A impedance analyzer or equivalent.
Unit Test Conditions/Comments
Mbps
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
50 MHz clock input3 (see Figure 25)
100 Mbps 215 − 1 PRBS input5
(see Figure 28)
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
ns CL = 15 pF (see Figure 29, Figure 32)
ns CL = 15 pF (see Figure 29, Figure 32)
CL = 15 pF (see Figure 29, Figure 32)
ps
ps
ns CL = 15 pF (see Figure 29, Figure 32)
ps 50 MHz clock input3 (see Figure 31)
100 Mbps 215 − 1 PRBS input5
(see Figure 34)
ps
ps
ns See Figure 30, Figure 33
ns See Figure 30, Figure 33
ns See Figure 30, Figure 33
ns See Figure 30, Figure 33
Rev. A | Page 5 of 20
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
A/Y
3.32kΩ
VTEST = –1V TO +3.4V
DI
VOD
49.9Ω
+
3.32kΩ
B/Z VTEST
–
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS.
Figure 18. Driver Voltage Measurement over Common-Mode Range
A/Y
DI
B/Z
C1 R1
1pF 24.9Ω
R2
24.9Ω
C2
1pF
C3
2.5pF VOC
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
<2cm FROM DUT.
Figure 19. Driver Common-Mode Output Voltage Measurement
VCC
S1
A/Y
DE B/Z
S2
VA(O), VB(O),
VY(O) OR VZ(O)
R1
1.62kΩ
±1%
Figure 20. Maximum Steady-State Output Voltage Measurement
VCC
A/Y
DI
S1
IOS
S2
B/Z
VTEST = –1V OR +3.4V
VTEST
Figure 21. Driver Short Circuit
A ≈ 1.3V
B ≈ 0.7V
VOC
VOC(PP)
ΔVOC(SS)
NOTES
1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. VOC(PP) MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 22. Driver Common-Mode Output Voltage (Steady State)
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Rev. A | Page 11 of 20
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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