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PDF W6811 Data sheet ( Hoja de datos )
| Número de pieza | W6811 | |
| Descripción | SINGLE CHANNEL VOICECODEC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de W6811 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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W6811 SINGLE CHANNEL
VOICECODEC
1. GENERAL DESCRIPTION
The W6811 is a general-purpose single channel PCM CODEC with pin-selectable u-Law or A-Law companding.
The device is compliant with the ITU G.712 specification. It operates off of separated analog (5V) and digital (3V)
power supplies and is available in 24-pin SOG, and SSOP package options. Functions performed include
digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems.
The filters are compliant with ITU G.712 specification. W6811 performance is specified over the industrial
temperature range of –40C to +85C.
The W6811 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving
300 loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise
and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-
frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN
applications. W6811 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-
scaler automatically determines the division ratio for the required internal clock.
2. FEATURES
Power supply:
Analog 4.5 – 5.5V
Digital 2.7 – 3.3V
Typical power dissipation of 25 mW, power-
down mode of 0.5 W
Fully-differential analog circuit design
On-chip precision reference of 1.575 V for a 0
dBm TLP at 600
Push-pull power amplifiers with external gain
adjustment with 300 load capability
Seven master clock rates of 256 kHz to 4.096
MHz
Pin-selectable -Law and A-Law companding
(compliant with ITU G.711)
CODEC A/D and D/A filtering compliant with
ITU G.712
Industrial temperature range (–40C to +85C)
Package: 24-pin SOG, and SSOP
Pb-Free / RoHS package options available
Applications
Digital Telephone Systems
Central Office Equipment (Gateways, Switches,
Routers)
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PBX Systems (Gateways, Switches)
PABX/SOHO Systems
Local Loop card
SOHO Routers
VoIP Terminals
Enterprise Phones
ISDN Terminals
Analog line cards
Digital Voice Recorders
Revision A15
-1-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
W6811 SINGLE CHANNEL
VOICECODEC
6. PIN DESCRIPTION
Pin
Name
VREF
RO-
Pin No.
SSOP
SOP
1
VDD*
Functionality
A
This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA
through a 0.1 F ceramic decoupling capacitor. No external loads should be tied to this pin.
2
A
Inverting output of the receive smoothing filter. This pin can typically drive a 2 k load to 1.575
volt peak referenced to the analog ground level.
PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
PAO+
VDDA
4
A
Inverting power amplifier output. This pin can drive a 300 load to 1.575 volt peak referenced to
the VAG voltage level.
5
A
Non-inverting power amplifier output. This pin can drive a 300 load to 1.575 Volt peak
referenced to the VAG voltage level.
6 A Analog power supply. This pin should be decoupled to VSSA with a 0.1F ceramic capacitor.
NC 7
Not Connected
VDDD
FSR
PCMR
8
D
Digital power supply. This pin should be decoupled to VSSD with a 0.1F ceramic capacitor. For
correct operation, VDDD value should always be lower than VDDA.
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel
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9 D 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive
are synchronous operations.
10 D PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
BCLKR 11 D selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
12
D
Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD,
the part is powered down.
MCLK
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
13
D
kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the
MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of
256 and 512 kHz frequencies.
BCLKT
14 D PCM transmit bit clock input pin.
PCMT
15 D PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
Revision A15
-5-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
W6811 SINGLE CHANNEL
VOICECODEC
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame sync cycles.
It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC
(FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit
and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC
pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh
positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative
edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative
edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channels. For more timing information, see
the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock
rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if
desired. An internal pre-scaler is used to generate a fixed 256 kHz and an 8 kHz sample clock for the internal
CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the
division ratio accordingly. If the Frame Sync is LOW for the entire frame sync period while the MCLK and BCLK
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pin clock signals are still present, the W6811 will enter the low power standby mode. Another way to power down
is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to
HIGH and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
Revision A15
- 11 -
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet W6811.PDF ] | |
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