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PDF NAU8501 Data sheet ( Hoja de datos )
| Número de pieza | NAU8501 | |
| Descripción | 24-Bit Stereo Audio ADC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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NAU8501
Description
NAU8501 Data Sheet
24-bit Stereo Audio ADC with Differential Microphone Inputs
emPowerAudio™
The NAU8501 is a low power, high quality audio input system for portable applications. In addition to precision
24-bit stereo ADCs, this device integrates a broad range of additional functions to simplify implementation of
complete audio systems. The NAU8501 includes low-noise stereo differential high gain microphone inputs with
wide range programmable amplifiers, separate line inputs, and an analog bypass/sidetone line level stereo output.
Advanced on-chip digital signal processing includes a limiter/ALC (Automatic Level Control), 5-band equalizer,
notch filter, and a high-pass filter for speech optimization and wind noise reduction. The digital interface can
operate as either a master or a slave. Additionally, an internal fractional-N PLL is available to accurately
generate any audio sample rate clock for the ADCs derived using any available system clock from 8MHz
through 33MHz.
The NAU8501 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate as low
as 1.7V to conserve power. Internal control registers enable flexible power conserving modes, shutting down or
reducing power in sub-sections of the chip under software control.
The NAU8501 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is
available upon request.
Key Features
ADC: 90dB SNR and -80dB THD (“A” weighted)
Stereo differential input microphone amplifiers
Very wide range programmable input amplifier
Stereo line inputs with gain options and mixing
Stereo line outputs with gain control and mute
On-chip high resolution fractional-N PLL
Integrated DSP with specific functions:
5-band equalizer
High pass filter / wind noise reduction
Automatic level control / limiter
Programmable notch filter
Serial control interfaces with read/write capability
Standard audio interfaces: PCM and I2S
Supports any sample rate from 8kHz to 48kHz
Read/Write control register interface
Applications
Audio Recording Devices
Security Systems
Video and Still Cameras
Enhanced Audio Inputs for SOC products
Audio Input Accessory Products
Gaming Systems
NAU8501 Data Sheet Rev1.8
Page 1 of 80
Feb, 2014
1 page  
NAU8501
Electrical Characteristics
Conditions: VDDC = 1.8V, VDDA = VDDB = VDDA2 = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz,
24-bit audio data, 64X oversampling rate, unless otherwise stated.
Parameter
Symbol Comments/Conditions Min Typ Max Units
Analog to Digital Converter (ADC)
Full scale input signal 1
VINFS
PGABST = 0dB
PGAGAIN = 0dB
1.0 Vrms
0 dBV
Signal-to-noise ratio
Total harmonic distortion 2
SNR Gain = 0dB, A-weighted
THD+N Input = -3dB FS input
tbd 90
dB
-80 tbd dB
Channel separation
1kHz input signal
103 dB
Microphone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) and Programmable Gain Amplifier (PGA)
Full scale input signal 1
PGABST = 0dB
1.0 Vrms
PGAGAIN = 0dB
0 dBV
Programmable gain
-12
35.25
dB
Programmable gain step size
Guaranteed Monotonic
0.75 dB
Mute Attenuation
120 dB
Input resistance
Inverting Input
PGA Gain = 35.25dB
PGA Gain = 0dB
PGA Gain = -12dB
Non-inverting Input
1.6 kΩ
47 kΩ
75 kΩ
94 kΩ
Line Inputs
Line Path Gain = +6dB 20 kΩ
Line In Gain = 0dB
40 kΩ
Line In Gain = -12dB
159 kΩ
Input capacitance
10 pF
PGA equivalent input noise
0 to 20kHz, Gain set to
120 µV
35.25dB
Input Boost Mixer
Gain boost
Boost disabled
0 dB
Boost enabled
20 dB
Line Input to boost/mixer gain
-12 6 dB
Line Input step size to boost/mixer
3 dB
Microphone Bias
Bias voltage
VMICBIAS See Figure 3
0.50, 0.60,0.65, 0.70,
0.75, 0.85, or 0.90
VDDA
VDDA
Bias current source
Output noise voltage
IMICBIAS
Vn
1kHz to 20kHz
3 mA
14 nV/√Hz
NAU8501 Data Sheet Rev1.8
Page 5 of 80
Feb, 2014
5 Page 
NAU8501
1.1.3 ADC Function and Digital Signal Processing
Each left and right channel has an independent high quality ADC associated with it. These are high performance,
24-bit delta-sigma converters that are suitable for a very wide range of applications.
Each ADC is supported by an analog input mixer to select/mix the inputs available to that ADC. The output of
the ADC is supported by an advanced digital signal processing subsystem (DSP) that enables a very wide range
of programmable signal conditioning and signal optimizing functions. All digital processing is with 24-bit
precision, as to minimize processing artifacts and maximize the audio dynamic range supported by the
NAU8501.
The available DSP features include a wide range, mixed-mode Automatic Level Control (ALC), a high pass
filter, a notch filter, scaling in decibels, and a digital mute function. All of these features are optional and highly
programmable. The high pass filter function includes a very low frequency DC-blocking feature, or optionally,
an application mode feature for low frequency audio noise reduction, such as to reduce unwanted ambient noise
or “wind noise” on a microphone input. The notch filter may be programmed over a very wide frequency range
and notch depth to greatly reduce a specific frequency band or frequency. Typically, this is used to reject a
certain frequency such as a 50Hz, 60Hz, or 217Hz unwanted noise, but may also be used to eliminate an
unwanted housing resonance or noise such as from camera motors.
Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer.
These features are optional, and are programmable over wide ranges.
1.1.4 Digital Interfaces
Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This
is a simple, but highly flexible interface that is compatible with many commonly used command and control
serial data protocols and host drivers.
Digital audio input/output data streams are transferred to and from the device separately from command and
control. The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with
commonly used industry standard devices that follow either of these two serial data formats.
1.1.5 Clock Requirements
The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided
externally, or by optional operation of a built-in PLL (Phase Locked Loop).
The PLL is provided as a low cost, zero external component count optional method to generate required clocks
in almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired
audio sample rates derived from a very wide range of commonly available system clocks.
The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the
range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit
value, any desired sample rate supported by the NAU8501 can be generated with very high accuracy, typically
limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these
ranges are also possible, but may involve performance tradeoffs and increased design verification.
NAU8501 Data Sheet Rev1.8
Page 11 of 80
Feb, 2014
11 Page | ||
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| PDF Descargar | [ Datasheet NAU8501.PDF ] | |
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