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W949D6CB fiches techniques PDF

Winbond - (W949D2CB / W949D6CB) 512Mb Mobile LPDDR

Numéro de référence W949D6CB
Description (W949D2CB / W949D6CB) 512Mb Mobile LPDDR
Fabricant Winbond 
Logo Winbond 





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W949D6CB fiche technique
www.DataSheet.co.kr
W949D6CB / W949D2CB
512Mb Mobile LPDDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ................................................................................................. 4
2. FEATURES ......................................................................................................................... 4
3. PIN CONFIGURATION ....................................................................................................... 5
3.1 Ball Assignment: LPDDR X16 .................................................................................................. 5
3.2 Ball Assignment: LPDDR X32 .................................................................................................. 5
4. PIN DESCRIPTION ............................................................................................................. 6
4.1 Signal Descriptions................................................................................................................... 6
4.2 Addressing Table ..................................................................................................................... 7
5. BLOCK DIAGRAM.............................................................................................................. 8
5.1 Block Diagram.......................................................................................................................... 8
5.2 Simplified State Diagram .......................................................................................................... 9
6. FUNCTION DESCRIPTION ...............................................................................................10
6.1 Initialization ............................................................................................................................ 10
6.1.1 Initialization Flow Diagram .............................................................................................................11
6.1.2 Initialization Waveform Sequence ..................................................................................................12
6.2 Register Definition .................................................................................................................. 12
6.2.1 Mode Register Set Operation.........................................................................................................12
6.2.2 Mode Register Definition ................................................................................................................13
6.2.3. Burst Length ..................................................................................................................................13
6.3 Burst Definition....................................................................................................................... 14
6.4 Burst Type.............................................................................................................................. 15
6.5 Read Latency ......................................................................................................................... 15
6.6 Extended Mode Register Description ..................................................................................... 15
6.6.1 Extended Mode Register Definition................................................................................................16
6.7 Status Register Read ............................................................................................................. 16
6.7.1 SRR Register (A[n:0] = 0) ..............................................................................................................17
6.7.2 Status Register Read Timing Diagram...........................................................................................18
6.8 Partial Array Self Refresh ....................................................................................................... 19
6.9 Automatic Temperature Compensated Self Refresh............................................................... 19
6.10 Output Drive Strength........................................................................................................... 19
6.11 Commands........................................................................................................................... 19
6.11.1 Basic Timing Parameters for Commands ....................................................................................19
6.11.2 Truth Table - Commands .............................................................................................................20
6.11.3 Truth Table - DM Operations .......................................................................................................21
6.11.4 Truth Table - CKE ........................................................................................................................21
6.11.5 Truth Table - Current State BANKn - Command to BANKn.........................................................22
6.11.6 Truth Table - Current State BANKn, Command to BANKn..........................................................23
7. OPERATION ......................................................................................................................24
7.1. Deselect ................................................................................................................................ 24
7.2. No Operation......................................................................................................................... 24
7.2.1 NOP Command ..............................................................................................................................25
-1-
Publication Release Date: Sep, 21, 2011
Revision A01-007
Datasheet pdf - http://www.DataSheet4U.net/

PagesPages 60
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