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PDF W39V040FB Data sheet ( Hoja de datos )
| Número de pieza | W39V040FB | |
| Descripción | 512K X 8 CMOS FLASH MEMORY | |
| Fabricantes | Winbond | |
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W39V040FB Data Sheet
Table of Contents-
512K × 8 CMOS FLASH MEMORY
WITH FWH INTERFACE
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................ 4
4. BLOCK DIAGRAM ...................................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 4
6. FUNCTIONAL DESCRIPTION ................................................................................................... 5
6.1 Interface Mode Selection and Description..................................................................... 5
6.2 Read (Write) Mode ........................................................................................................ 5
6.3 Reset Operation............................................................................................................. 5
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ....................... 5
6.5 Sector Erase Command ................................................................................................ 6
6.6 Program Operation ........................................................................................................ 6
6.7 Hardware Data Protection ............................................................................................. 6
6.8 WRITE OPERATION STATUS...................................................................................... 6
7. REGISTER FOR FWH MODE .................................................................................................... 8
7.1 General Purpose Inputs Register for FWH Mode.......................................................... 8
7.2 Product Identification Registers..................................................................................... 8
7.3 Block Locking Registers ................................................................................................ 8
7.4 Register Based Block Locking Value Definitions Table ................................................ 9
7.5 Read Lock.................................................................................................................... 10
7.6 Write Lock .................................................................................................................... 10
7.7 Lock Down ................................................................................................................... 10
7.8 Product Identification Registers................................................................................... 10
8. TABLE OF OPERATING MODES ............................................................................................ 11
8.1 Operating Mode Selection - Programmer Mode.......................................................... 11
8.2 Operating Mode Selection - FWH Mode ..................................................................... 11
8.3 FWH Cycle Definition................................................................................................... 11
9. TABLE OF COMMAND DEFINITION ....................................................................................... 12
9.1 Embedded Programming Algorithm ............................................................................ 13
9.2 Embedded Erase Algorithm......................................................................................... 14
9.3 Embedded #Data Polling Algorithm............................................................................. 15
9.4 Embedded Toggle Bit Algorithm.................................................................................. 16
9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow . 17
Publication Release Date: December 12, 2005
- 1 - Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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W39V040FB
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is
FWH interface mode. The IC (Mode) pin of the device provides the control between these two
interface modes. These interface modes need to be configured before power up or return from
#RESET. When IC (Mode) pin is set to VDD, the device will be in the Programmer mode; while the IC
(Mode) pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer
mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column
address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11].
And the column address are mapped to the lower internal address A[10:0]. For FWH mode, it
complies with the FWH Interface Specification, through the FWH[3:0] to communicate with the system
chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040FB is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined
by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for
further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on
programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased.
If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software
command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address
7FFF2(hex). You can check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is
in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition,
whether boot block can be programmed/erased or not will depend on software setting. On the other
hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter
how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it
means the #WP pin is in high state, then all the sectors except the boot block can be
programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block
are programmed/erased inhibited.
Publication Release Date: December 12, 2005
- 5 - Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
W39V040FB
8. TABLE OF OPERATING MODES
8.1 Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
#OE
VIL
VIH
X
VIL
X
VIH
#WE
VIH
VIL
X
X
VIH
X
#RESET
VIH
VIH
VIL
VIH
VIH
VIH
PINS
ADDRESS
AIN
AIN
X
X
X
X
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
8.2 Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected.
When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".
8.3 FWH Cycle Definition
FIELD
START
IDSEL
MSIZE
TAR
ADDR
SYNC
DATA
NO. OF
CLOCKS
1
1
1
2
7
N
2
DESCRIPTION
"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle. 0000b" appears on FWH bus to indicate the initial
This one clock field indicates which FWH component is being selected.
Memory Size. There is always show “0000b” for single byte access.
Turned Around Time
Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and
Address[3:0] on FWH[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble
first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then
DQ[7:4] on FWH[3:0] last.)
- 11 -
Publication Release Date: December 12, 2005
Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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