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PDF ICS9UMS9633BI Data sheet ( Hoja de datos )
| Número de pieza | ICS9UMS9633BI | |
| Descripción | ULTRA MOBILE PC CLOCK | |
| Fabricantes | IDT | |
| Logotipo |  |
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Advance Information
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL
TEMPERATURE RANGE
ICS9UMS9633BI
Recommended Application:
Poulsbo Based Ultra-Mobile PC (UMPC) for Industrial
Temperature Range
Output Features:
• 3 - CPU low power differential push-pull pairs
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
Features/Benefits:
• Industrial temperature range compliant
• Supports ULV CPUs with 67 to 167 MHz
CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO operation, 3.3V VDD core and
REF supply pin for REF
• -40 to +85C operating range
SSOP Pin Configuration
REF 1
GNDREF 2
VDDCORE_3.3 3
FSC_L 4
TEST_MODE 5
TEST_SEL 6
SCLK 7
SDATA 8
VDDCORE_3.3 9
VDDIO_1.5 10
DOT96C_LPR 11
DOT96T_LPR 12
GNDDOT 13
GNDLCD 14
LCD100C_LPR 15
LCD100T_LPR 16
VDDIO_1.5 17
VDDCORE_3.3 18
*CR#0 19
GNDSRC 20
SRCC0_LPR 21
SRCT0_LPR 22
*CR#1 23
VDDCORE_3.3 24
48 VDDREF_3.3
47 X1
46 X2
45 CLKPWRGD#/PD_3.3
44 CPU_STOP#
43 CPUT0_LPR
42 CPUC0_LPR
41 VDDIO_1.5
40 GNDCPU
39 CPUT1_LPR
38 CPUC1_LPR
37 VDDCORE_3.3
36 VDDIO_1.5
35 GNDCPU
34 CPUT2_LPR
33 CPUC2_LPR
32 FSB_L
31 *CR#2
30 SRCT2_LPR
29 SRCC2_LPR
28 GNDSRC
27 SRCT1_LPR
26 SRCC1_LPR
25 VDDIO_1.5
48 SSOP Package
* indicates inputs with internal pull up of ~10Kohm to 3.3V
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
1
1451—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
Advance Information
MLF Pin Description
PIN #
PIN NAME
1 CPU_STOP#
2 CLKPWRGD#/PD_3.3
3 X2
4 X1
5 VDDREF_3.3
6 REF
7 GNDREF
8 VDDCORE_3.3
9 FSC_L
10 TEST_MODE
11 TEST_SEL
12 SCLK_3.3
13 SDATA_3.3
14 VDDCORE_3.3
15 VDDIO_1.5
16 DOT96C_LPR
17 DOT96T_LPR
18 GNDDOT
19 GNDLCD
20 LCD100C_LPR
21 LCD100T_LPR
22 VDDIO_1.5
23 VDDCORE_3.3
24 *CR#0
TYPE
DESCRIPTION
IN Stops all CPU clocks, except those set to be free running clocks
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
IN are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
OUT
IN
PWR
OUT
PWR
PWR
IN
IN
IN
IN
I/O
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
IN
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Power pin for the XTAL and REF clocks, nominal 3.3V
14.318 MHz reference clock.
Ground pin for the REF outputs.
3.3V power for the PLL core
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V power for the PLL core
Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
Ground pin for DOT clock output
Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
Power supply for low power differential outputs, nominal 1.5V.
3.3V power for the PLL core
Clock request for SRC0, 0 = enable, 1 = disable
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
5
1451—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
Advance Information
Table 1: CPU Frequency Select Table
FSLC1 FSLB1
CPU
MHz
SRC
MHz
DOT
MHz
LCD REF
MHz MHz
0 0 133.33
0 1 166.67
100.00 96.00 100.00 14.318
1 0 100.00
1 1 66.67
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
Table 2: LCD Spread Select Table (Pin 20/21)
B1b5 B1b4
B1b3 Spread Comment
%
00
0 -0.5% LCD100
00
1 -1% LCD100
01
0 -2% LCD100
01
1 -2.5% LCD100
10
0 +/- 0.25% LCD100
10
1 +/-0.5% LCD100
11
0 +/-1% LCD100
11
1 +/-1.25% LCD100
Table 3: CPU N-step Programming
CPU
(MHz)
P Default N
(hex)
Fcpu
133.33 3 64 = 4MHz x N/P
166.67 3 7D = 4MHz x N/P
100.00 4 64 = 4MHz x N/P
200.00 2 64 = 4MHz x N/P
CPU Power Management Table
PD CPU_STOP# SMBus Register
OE
01
Enable
1X
Enable
00
Enable
0X
Disable
CPU
Running
Low/20K
High
Low/20K
CPU#
Running
Low
Low
Low
SRC, LCD, DOT Power Management Table
SMBus Register
PD CR_x#
OE SRC SRC# DOT/LCD DOT#/LCD#
00
1X
01
0X
Enable
X
Enable
Disable
Running Running
Low/20K Low
Low/20K Low
Low/20K Low
Running
Low/20K
Running
Low/20K
Running
Low
Running
Low
REF Power Management Table
PD
SMBus Register
OE
REF
0 Enable
1X
0 Disable
Running
Low
Low
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range
11
1451—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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