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PDF 72720YV Data sheet ( Hoja de datos )
| Número de pieza | 72720YV | |
| Descripción | Single-Chip RDS Signal-Processing System IC | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : ENN6488
CMOS IC
LC72720Y, 72720YV
Single-Chip RDS
Signal-Processing System IC
Overview
The LC72720Y and LC72720YV are single-chip system
ICs that implement the signal processing required by the
European Broadcasting Union RDS (Radio Data System)
standard and by the US NRSC (National Radio System
Committee) RDBS (Radio Broadcast Data System)
standard. These ICs include band-pass filter, demodulator,
synchronization, and error correction circuits as well as
data buffer RAM on chip and perform effective error
correction using a soft-decision error correction technique.
Functions
• Band-pass filter: Switched capacitor filter (SCF)
• Demodulator: RDS data clock regeneration and
demodulated data reliability information
• Synchronization: Block synchronization detection (with
variable backward and forward protection conditions)
• Error correction: Soft-decision/hard-decision error
correction
• Buffer RAM: Adequate for 24 blocks of data (about 500
ms) and flag memory
• Data I/O: CCB interface (power on reset)
Features
• Error correction capability improved by soft-decision
error correction.
• The load on the control microprocessor can be reduced
by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide
continuous and stable detection of the synchronization
timing.
• Data can be read out starting with the backward-
protection block data after a synchronization reset.
• Fully adjustment free.
• Low voltage (supply voltage: 3.0 V min) type.
• Operating power-supply voltage: 3.0 to 3.6 V
• Operating temperature: –40 to +85°C
• Package: DIP24S, SSOP30
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42800TN (OT) No. 6488-1/14
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1 page  
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LC72720Y, 72720YV
Continued from preceding page.
Parameter
Group delay deviation
Reference voltage output
Hysteresis
Output low-level voltage
Input high-level current
Input low-level current
Output off leakage current
Current drain
Symbol
Conditions
G-Delay
Vref
VHIS
VOL1
VOL2
IIH1
IIH2
IIL1
IIL2
IOFF
IDD
FLOUT: f = 57 ± 1.2 kHz
VREF : Vdda = 3.3 V
CL, DI, CE, SYR, T1, T2
DO, T3, T4, T5, T6, T7 : I = 2 mA
SYNC, RDS-ID : I = 8 mA
CL, DI, CE, SYR, T1, T2 : VI = Vddd
XIN : VI = Vddd
CL, DI, CE, SYR, T1, T2 : VI = 0 V
XIN : VI = 0 V
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :
VO = 6.5 V
Vddd + Vdda, Vddd = Vdda = 3.3 V
Ratings
min typ
1.65
0.1 Vddd
0.9
0.9
6
max
± 2.0
0.5
0.5
5.0
4.0
5.0
4.0
5.0
Unit
μs
V
V
V
V
μA
μA
μA
μA
μA
mA
CCB Output Data Format
• Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
• Any number of 32-bit output data blocks can be output consecutively.
• When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
• If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to reread that whole block.
• The check bits (10 bits) are not output.
• The data valid / invalid decision is made by referencing the error information flag (E0 to E2) but the offset word
detection flag (OWD) must not be referred to.
• When the first leading bits are not “1010”, the read in data is invalid, and the read operation is cancelled.
CCB address 6C
B0 B1 B2 B3 A0 A1 A2 A3
DI
00110110
Output data/first bit
Last bit
DO 1 0 1 0 OWD B2 B1 B0 RE RF1 RF0 ARI SYC E2 E1 E0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(1) Offset word detection flag (1 bit): OWD
OWD
1
0
Offset word detection
Detected
Not detected (protection function operating)
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI (SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
A13207
No. 6488-5/14
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LC72720Y, 72720YV
Serial Data Input and Output Methods
Data is input and output using the CCB (computer control bus), which is the Sanyo audio IC serial bus format. This IC
adopts an 8-bit address CCB format.
(LSB)
Address
(MSB)
I/O mode
B0 B1 B2 B3 A0 A1 A2 A3
Comment
1
IN1 (6A)
0
1
0
1
0
1
1
0
· Control data input mode, also referred to as “serial data input” mode.
· This is a 16-bit data input mode.
2
IN2 (6B)
1
1
0
1
0
1
1
0
· Control data input mode, also referred to as “serial data input” mode.
· This is a 16-bit data input mode.
3
OUT (6C)
0
0
1
1
0
1
1
0
· Data output mode, also referred to as “serial data output” mode.
· The data for multiple blocks can be output sequentially in this mode.
I/O mode determined
CE
1
CL
2
DI B0 B1 B2 B3 A0 A1 A2
1
DO
2
➀ For the CL normal high state
➁ For the CL normal low state
A3
First Data IN1/2
First Data OUT
First Data OUT
A13212
Serial data input (IN1, IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 μs tLC < 1.15μs tCE < 20 ms
CL: Normal high
CE
CL
DI
Internal data
tEL tES tCE tEH
tSU tHD
B0 B1 B2 B3 A0 A1 A2
A3
FS0 FS1 FS2 FS3
CT1 0
0
0
EC3 EC4 CT0 0
TS0 TS1 TS2 TS3
tLC
A13213
CL: Normal low
tEL tES tCE tEH
CE
CL
tSU tHD
DI
B0 B1 B2 B3 A0 A1 A2 A3
FS0
CT1
FS1 FS2 FS3
0 00
Internal data
EC3 EC4 CT0 0
TS0 TS1 TS2 TS3
tLC
A13214
No. 6488-11/14
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