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PDF NL4823BC37-05 Data sheet ( Hoja de datos )
| Número de pieza | NL4823BC37-05 | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL4823BC37-05
18cm (7.0wide Type)
WQVGA
PRELIMINARY DATA SHEET
DOD-PP-0014 (3rd edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-MD-0086(2).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PP-0014 (3rd edition)
Published date: July 2006 CP(N)
1 © NEC LCD Technologies, Ltd.
2006 All rights reserved.
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NL4823BC37-05
2. GENERAL SPECIFICATIONS
Display area
154.08 (H) × 87.048 (V) mm
Diagonal size of display 18cm (7.0inches)
Drive system
a-Si TFT active matrix
Display color
262,144 colors
Pixel
480 (H) × 234 (V) pixels
Pixel arrangement
RGB (Red dot, Green dot, Blue dot) vertical stripe
Dot pitch
0.107 (H) × 0.372 (V) mm
Pixel pitch
0.321 (H) × 0.372 (V) mm
Module size
174.5 (W) × 105.5 (H) × 10.5 (D) mm (typ.)
Weight
205g (typ.)
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
600:1 (typ.)
At the contrast ratio ≥10:1
• Horizontal: Right side 80° (typ.), Left side 80° (typ.)
• Vertical: Up side 60° (typ.), Down side 80° (typ.)
At DPS= Low or open: Normal scan
• Viewing direction without image reversal: down side (6 o'clock)
• Viewing direction with contrast peak: up side (12 o'clock)
• Viewing angle with optimum grayscale (γ=2.2): normal axis
(perpendicular)
Clear
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
3H (min.) [by JIS K5400]
At LCD panel center
40% (typ.) [against NTSC color space]
Ton+Toff (10% ←→ 90%)
25 ms (typ.)
At IBL= 6.0mArms / lamp
400cd/m2 (typ.)
6-bit digital signals for data of RGB colors,
Dot clock (CLK), Data enable (DE)
LCD panel signal processing board: 3.3V
Edge light type: 1 cold cathode fluorescent lamp
Backlight
Replaceable part
• Lamp holder set: Type No. TBD
Power consumption
Recommended inverter (Option)
• Inverter: Type No. 70PW021
At IBL= 6.0mArms / lamp, Checkered flag pattern
TBD W (typ., Power dissipation of the inverter is not included.)
PRELIMINARY DATA SHEET DOD-PP-0014 (3rd edition)
5
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4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VCC
Note1
3.0V
0V
ON
Tr < 30ms
Display signals
Function signal
Note2
0V
0ms < t < 35ms
VALID period
NL4823BC37-05
OFF ON
Toff > 50ms
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V, a
protection circuit may work, and then this product may not work.
Note2: Display signals (CLK, DE, DATA (R0 to R5, G0 to G5, B0 to B5)) and function signal
(DPS) must be Low or High-impedance, exclude the VALID period (See above sequence
diagram), in order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. VCC should be cut
when the display and function signals are stopped.
4.4.2 Inverter (Option)
Display signals
Function signals
Note1
Note2
VALID period
VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-PP-0014 (3rd edition)
11
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