PDF FM31T374 Data sheet ( Hoja de datos )

Número de pieza	FM31T374
Descripción	(FM31T372 - FM31T378) System Supervisor & Temperature Compensated RTC
Fabricantes	Ramtron
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No Preview Available ! www.DataSheet.co.kr Preliminary FM31T372/374/376/378 System Supervisor & Temperature Compensated RTC (TCXO) with Embedded Crystal Features High Integration Device Replaces Multiple Parts  Real-time Clock (RTC) o Embedded 32.768kHz Crystal o Temperature Compensated  32.768 kHz Clock Output  Low-VDD Detection Drives Reset  Watchdog Timer  Early Power-Fail Warning/NMI  Two 16-bit Event Counters with Event Driven Interrupt Output  Serial Number with Write-lock for Security Ferroelectric Nonvolatile RAM  4Kb, 16Kb, 64Kb, and 256Kb versions  Unlimited Read/Write Endurance  10 year Data Retention  NoDelay™ Writes Real-time Clock/Calendar  Temp-Compensated Using On-Chip Sensor o  5 ppm over -40°C to +85°C o Accuracy  2 ½ min. per year  Backup Current 1.4 A (max.) at +25C  Seconds through Centuries in BCD format  Tracks Leap Years through 2099  No External Crystal Required  Offset Register to Correct for Crystal Aging  Supports Battery or Capacitor Backup Processor Companion  32.768 kHz Clock Output  Active-low Reset Output for VDD and Watchdog  Programmable VDD Reset Trip Point  Manual Reset Filtered and Debounced  Programmable Watchdog Timer  Dual Battery-backed Event Counter Tracks System Intrusions or other Events  Event Counter Driven Interrupt Output  Comparator for Early Power-Fail Interrupt  64-bit Programmable Serial Number with Lock Fast Two-wire Serial Interface  Up to 1 MHz Maximum Bus Frequency  Supports Legacy Timing for 100 kHz & 400 kHz  Device Select Pins for up to 4 Memory Devices  RTC, Supervisor Controlled via 2-wire Interface Easy to Use Configurations  Operates from 2.7 to 5.5V  Small Footprint 14-pin “Green” SOIC (-G)  Low Operating Current  -40C to +85C Operation Description The FM31T37x is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile F-RAM memory available in various sizes, temperature-compensated real-time clock with embedded crystal, 32.768kHz clock output, low-VDD reset, watchdog timer, battery backed event counter, event driven interrupt output, lockable 64-bit serial number area, general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose, and 2-wire serial interface to a host microcontroller. The family operates from 2.7 to 5.5V. The real-time clock (RTC) provides time and date information in BCD format. It can be permanently powered from external backup voltage source, either a battery or a capacitor. The timekeeper uses an internal 32.768 kHz crystal which is factory- calibrated for excellent timekeeping accuracy over the industrial temperature range. This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.1 Apr. 2011 The FM31T37x devices integrate 4Kb, 16Kb, 64Kb, and 256Kb of F-RAM memory. F-RAM offers superior write speed and unlimited endurance. This allows the memory to provide system data collection and as read/write RAM storage. This memory is truly nonvolatile rather than battery-backed. The processor companion includes commonly needed CPU support functions. Supervisory functions include a reset output signal controlled by either a low VDD condition or a watchdog timeout. /RST goes active when VDD drops below a programmable threshold and remains active for 100 ms after VDD rises above the trip point. A programmable watchdog timer runs from 100 ms to 3 seconds. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host before the timeout. A flag-bit indicates the source of the reset. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 26 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr The bits VTP1 and VTP0 control the trip point of the low voltage detect circuit. They are located in register 0Bh, bits 1 and 0. VTP 2.6V 2.9V 3.9V 4.4V VTP1 00 01 10 11 VTP0 The watchdog timer can also be used to assert the reset signal (/RST). The watchdog is a free running programmable timer. The period can be software programmed from 100 ms to 3 seconds in 100 ms increments via a 5-bit nonvolatile register. All programmed settings are minimum values and vary with temperature according to the operating specifications. The watchdog has two additional controls associated with its operation, a watchdog enable bit (WDE) and timer restart bits (WR). Both the enable bit must be set and the watchdog must timeout in order to drive /RST active. If a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. If WDE=0, the watchdog timer runs but a watchdog fault will not cause /RST to be asserted low. The WTR flag will be set, indicating a watchdog fault. This setting is useful during software development and the developer does not want /RST to drive. Note that setting the maximum timeout setting (11111b) disables the counter to save power. The second control is a nibble that restarts the timer preventing a reset. The timer should be restarted after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4-0, and the watchdog enable is bit 7. The watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. Writing this pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is free-running. Prior to enabling it, users should restart the timer as described above. This assures that the full timeout period will be set immediately after enabling. The watchdog is disabled when VDD is below VTP. The following table summarizes the watchdog bits. A block diagram follows. Watchdog timeout Watchdog enable Watchdog restart WDT4-0 0Ah, bits 4-0 WDE 0Ah, bit 7 WR3-0 09h, bits 3-0 FM31T372/374/376/378-G 100 ms clock Timebase WR3-0 = 1010b to restart Counter /RST Watchdog timeout WDE Figure 3. Watchdog Timer Manual Reset The /RST pin is bi-directional and allows the FM31T37x to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms. A manual reset does not set any flags. MCU RST Reset Switch FM31T37x Switch Behavior RST FM31T37x drives 100 ms (min.) Figure 4. Manual Reset Note that an internal weak pull-up on /RST eliminates the need for additional external components. Reset Flags In case of a reset condition, a flag will be set to indicate the source of the reset. A low VDD reset is indicated by the POR flag, register 09h bit 6. A watchdog reset is indicated by the WTR flag, register 09h bit 7. Note that the flags are internally set in response to reset sources, but they must be cleared by the user. When the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. Early Power Fail Comparator An early power fail warning can be provided to the processor well before VDD drops out of spec. The comparator is used to create a power fail interrupt (NMI). This can be accomplished by connecting the PFI pin to the unregulated power supply via a resistor divider. An application circuit is shown below. Rev. 1.1 Apr. 2011 Page 5 of 26 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr FM31T372/374/376/378-G Register Map The TCXO and processor companion functions are accessed via 25 special function registers mapped to a separate 2-wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or information flags. A description of each register follows the summary table below. Register Map Summary Table Nonvolatile = Battery-backed = Address 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h D7 SNL WDE W TR 0 0 0 0 0 0 /OSCEN reserved Data D6 D5 D4 D3 Serial Number Byte 7 Serial Number Byte 6 Serial Number Byte 5 Serial Number Byte 4 Serial Number Byte 3 Serial Number Byte 2 Serial Number Byte 1 Serial Number Byte 0 Counter 2 MSB Counter 2 LSB Counter 1 MSB Counter 1 LSB RC FOEN FC WP1 WP0 - - WDT4 W DT3 POR LB - WR3 10 years 00 10 mo 0 10 date 00 00 0 10 hours 10 minutes 10 seconds CALS CAL5 CAL4 CAL3 CF reserved reserved reserved D2 D1 CC C2P VBC VTP1 WDT2 WDT1 WR2 WR1 years months date day hours minutes s econds CAL2 CAL1 CAL W D0 C1P VTP0 WDT0 WR0 CAL0 R Function Range Serial Number 7 FFh Serial Number 6 FFh Serial Number 5 FFh Serial Number 4 FFh Serial Number 3 FFh Serial Number 2 FFh Serial Number 1 FFh Serial Number 0 FFh Event Counter 2 MSB FFh Event Counter 2 LSB FFh Event Counter 1 MSB FFh Event Counter 1 LSB FFh Event Count Control Companion Control Watchdog Control Watchdog Restart/Flags Years 00-99 Month 1-12 Date 1-31 Day 1-7 Hours 0-23 Minutes 0-59 Seconds 0-59 OSC/CAL Control RTC Control Note: When the device is first powered up and programmed, all registers must be written because the battery-backed register values cannot be guaranteed. The table below shows the default values of the non-volatile registers. All other register values should be treated as unknown. Default Register Values Address Hex Value 18h 0x00 17h 0x00 16h 0x00 15h 0x00 14h 0x00 13h 0x00 12h 0x00 11h 0x00 0Bh 0x40 0Ah 0x1F 01h Factory programmed Rev. 1.1 Apr. 2011 Page 11 of 26 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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