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PDF FM3130 Data sheet ( Hoja de datos )
| Número de pieza | FM3130 | |
| Descripción | Integrated RTC/Alarm and 64Kb F-RAM | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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FM3130
Integrated RTC/Alarm and 64Kb F-RAM
Features
Real-time Clock/Calendar
High Integration Device Replaces Multiple Parts
Backup Current under 1 A
Serial Nonvolatile Memory
Seconds through Centuries in BCD format
Real-time Clock (RTC) with Alarm
Tracks Leap Years through 2099
Clock Output (Programmable frequency)
Uses Standard 32.768 kHz Crystal (12.5pF)
Software Calibration
64Kb Ferroelectric Nonvolatile RAM
Supports Battery or Capacitor Backup
Internally Organized as 8Kx8
Unlimited Read/Write Endurance
45 year Data Retention
NoDelay™ Writes
Fast Two-wire Serial Interface
E Up to 1 MHz Maximum Bus Frequency
Supports Legacy Timing for 100 kHz & 400 kHz
RTC & F-RAM Controlled via 2-wire Interface
T tDescription
nThe FM3130 integrates a real-time clock (RTC) and
E eF-RAM nonvolatile memory. The device operates
from 2.7 to 3.6V.
L em 4The FM3130 provides nonvolatile F-RAM which
c 6features fast write speed and unlimited endurance.
la 1This allows the memory to serve as extra RAM for
O p 3the system microcontroller or conventional
nonvolatile storage. This memory is truly nonvolatile
e Mrather than battery backed.
S R FThe real-time clock (RTC) provides time and date
t :information in BCD format. It can be permanently
c epowered from external backup voltage source, either
B ire tiva battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
D acalibration mode that allows software adjustment of
O No Alterntimekeeping accuracy.
Easy to Use Configurations
Operates from 2.7 to 3.6V
8-pin “Green” SOIC (-G) and TDFN (-DG)
Low Operating Current
Industrial Temperature -40C to +85C
Underwriters Laboratory (UL) Recognized
Pin Configuration
X1
X2
VBAK
VSS
1
2
3
4
8
7
6
5
VDD
ACS
SCL
SDA
X1
X2
VBAK
VSS
1 Top View 8
27
36
45
VDD
ACS
SCL
SDA
Pin Name
X1, X2
ACS
SDA
SCL
VBAK
VDD
VSS
Function
Crystal Connections
Alarm/Calibration/SqWave
Serial Data
Serial Clock
Battery-Backup Supply
Supply Voltage
Ground
Ordering Information
FM3130-G
“Green”/RoHS 8-pin SOIC
FM3130-GTR “Green”/RoHS 8-pin SOIC,
Tape & Reel
FM3130-DG “Green”/RoHS 8-pin TDFN
FM3130-DGTR “Green”/RoHS 8-pin TDFN,
Tape & Reel
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron‟s internal
qualification testing and has reached production status.
Rev. 3.2
Sept. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 22
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1 page  
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FM3130 Integrated RTC/Alarm with 64Kb FRAM
Vdd
FM3130
choose to drive X1 with an external clock and X2
with an inverted clock using a CMOS inverter.
Layout Recommendations
R1 The X1 and X2 crystal pins employ very high
X1 impedance circuits and the oscillator connected to
these pins can be upset by noise or extra loading. To
R2 reduce RTC clock errors from signal switching noise,
a guard ring should be placed around these pads and
Figure 3. External Oscillator
the guard ring grounded. SDA and SCL traces should
be routed away from the X1/X2 pads. The X1 and X2
trace lengths should be less than 5 mm. The use of a
In the example, R1 and R2 are chosen such that the
ground plane on the backside or inner board layer is
X2 voltage is centered around the oscillator drive
preferred. See layout example. Red is the top layer,
levels. If you wish to avoid the DC current, you may
green is the bottom layer.
EX1
TX2
tVBAK
nVSS
X1
X2
VBAK
VSS
LE eme 4Layout for Surface Mount Crystal
c 6(red = top layer, green = bottom layer)
Layout for Through Hole Crystal
(red = top layer, green = bottom layer)
O pla 31Table 2. Calibration Adjustments
e MPositive Calibration for slow clocks: Calibration will achieve 2.17 PPM after calibration
S R FMeasured Frequency Range
Error Range (PPM)
Min
Max
Min Max
Program Calibration Register to:
t :0 512.0000
511.9989
0 2.17
000000
c e1 511.9989
511.9967
2.18 6.51
100001
2 511.9967
511.9944
6.52 10.85
100010
B ire tiv3 511.9944
511.9922
10.86
15.19
100011
4 511.9922
511.9900
15.20
19.53
100100
D a5 511.9900
511.9878
19.54
23.87
100101
6 511.9878
511.9856
23.88
28.21
100110
O o rn7 511.9856
511.9833
28.22
32.55
100111
8 511.9833
511.9811
32.56
36.89
101000
N lte9 511.9811
511.9789
36.90
41.23
101001
10 511.9789
511.9767
41.24
45.57
101010
A11 511.9767
511.9744
45.58
49.91
101011
12 511.9744
511.9722
49.92
54.25
101100
13 511.9722
511.9700
54.26
58.59
101101
14 511.9700
511.9678
58.60
62.93
101110
15 511.9678
511.9656
62.94
67.27
101111
16 511.9656
511.9633
67.28
71.61
110000
17 511.9633
511.9611
71.62
75.95
110001
18 511.9611
511.9589
75.96
80.29
110010
19 511.9589
511.9567
80.30
84.63
110011
20 511.9567
511.9544
84.64
88.97
110100
21 511.9544
511.9522
88.98
93.31
110101
22 511.9522
511.9500
93.32
97.65
110110
23 511.9500
511.9478
97.66
101.99
110111
Rev. 3.2
Sept. 2011
Page 5 of 22
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5 Page 
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CALS
CAL.4-0
00h
LB
AF
CF
POR
AEN
CAL
W
R
FM3130 Integrated RTC/Alarm with 64Kb FRAM
Calibration Sign: Determines if the calibration adjustment is applied as an addition to or as a subtraction from
the time-base. This bit can be written only when CAL=1. Battery-backed, read/write.
Calibration Code: These five bits control the calibration of the clock. These bits can be written only when
CAL=1. Battery-backed, read/write.
RTC/Alarm Control
D7 D6
D5
D4 D3 D2 D1 D0
LB
AF
CF
POR
AEN
CAL
W
R
Low Battery Flag: If the VBAK source drops to a voltage level insufficient to operate the RTC/alarm, this bit
will be set to „1‟. All registers need to be re-initialized since the battery-backed register values should be
treated as unknown. The user should clear it to „0‟ when initializing the system. Battery-backed. Read/Write
(internally set, user can clear bit by writing to a „0‟).
Alarm Flag: This read-only bit is set to 1 when the time/date match the values stored in the alarm registers with
the Match bit(s) = 0. It is cleared when the RTC/Alarm Control register is read. Battery-backed.
Century Overflow Flag: This read-only bit is set to a 1 when the values in the years register overflows from 99
to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record
the new century information as needed. This bit is cleared when the RTC/Alarm Control register is read.
Battery-backed.
Power On Reset Flag: When VDD drops below VSW, the POR bit will be set to „1‟. Battery-backed.
Read/Write (internally set, user can clear bit by writing to a „0‟).
EAlarm Enable: This bit enables the alarm function. When AEN is set (and CAL cleared), the ACS pin operates
as an active-low alarm and the AF flag function is enabled. The function of the ACS pin is detailed in Table 3.
When AEN is cleared, no new alarm events will occur but the AF flag and ACS pin will not be cleared.
Battery-backed, read/write.
TCalibration Mode: When CAL is set to „1‟, the clock enters calibration mode. When CAL is set to „0‟, the clock
toperates normally, and the ACS pin is controlled by the RTC alarm. Battery-backed, read/write.
nWrite RTC: Setting the W bit to „1‟ freezes updates of the user timekeeping registers. The user can then write
E ethem with updated values. Setting the W bit to „0‟ causes the contents of the time registers to be transferred to
the timekeeping counters. Battery-backed, read/write.
mRead RTC: Setting the R bit to „1‟ copies a static image of the timekeeping core and place it into the user
L e 4registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from „0‟ to „1‟ causes the timekeeping capture, so the bit must be returned to „0‟ prior to reading again.
OBNoSDAilOrteecrnt aRtievpel:aFcM316Battery-backed,read/write.
Rev. 3.2
Sept. 2011
Page 11 of 22
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet FM3130.PDF ] | |
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