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PDF FM25L256B Data sheet ( Hoja de datos )
| Número de pieza | FM25L256B | |
| Descripción | 3V F-RAM Memory | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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www.DataSheet.co.kr
FM25L256B
256Kb FRAM Serial 3V Memory
Features
Write Protection Scheme
256K bit Ferroelectric Nonvolatile RAM
• Organized as 32,768 x 8 bits
• Hardware Protection
• Software Protection
• Unlimited Read/Write Cycles
• 45 Year Data Retention
• NoDelay™ Writes
Low Power Consumption
• Low Voltage Operation 2.7V – 3.6V
• Advanced High-Reliability Ferroelectric Process
Industry Standard Configurations
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
D• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
DEDescription
N SThe FM25L256B is a 256-kilobit nonvolatile
memory employing an advanced ferroelectric
E Nprocess. A ferroelectric random access memory or
FRAM is nonvolatile and performs reads and writes
M IGlike a RAM. It provides reliable data retention for 45
years while eliminating the complexities, overhead,
and system level reliability problems caused by
M S 2EEPROM and other nonvolatile memories.
O E V0Unlike serial EEPROMs, the FM25L256B performs
5write operations at bus speed. No write delays are
C D 2incurred. Data is written to the memory array
Mimmediately after each byte has been transferred to
Ethe device. The next bus cycle may commence
W : Fwithout the need for data polling. In addition, the
R E eproduct offers virtually unlimited write endurance.
tivFRAM also exhibits much lower power consumption
than EEPROM.
OT N rnaThese capabilities make the FM25L256B ideal for
nonvolatile memory applications requiring frequent
N R lteor rapid writes or low power operation. Examples
range from data collection, where the number of
O Awrite cycles may be critical, to demanding industrial
Fcontrols where the long write time of EEPROM can
• Industrial Temperature -40°C to +85°C
• 8-pin SOIC and 8-pin TDFN Packages
• “Green”/RoHS Packaging
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
/CS 1
SO 2
/WP 3
VSS 4
8 VDD
7 /HOLD
6 SCK
5 SI
Top View
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (2.7 to 3.6V)
Ground
cause data loss.
The FM25L256B provides substantial benefits to
users of serial EEPROM as a hardware drop-in
replacement. The FM25L256B uses the high-speed
SPI bus, which enhances the high-speed write
capability of FRAM technology. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
Ordering Information
FM25L256B-G*
“Green”/RoHS 8-pin SOIC
FM25L256B-GTR* “Green”/RoHS 8-pin SOIC
in Tape & Reel
FM25L256B-DG* “Green”/RoHS 8-pin TDFN
FM25L256B-DGTR* “Green”/RoHS 8-pin TDFN
in Tape & Reel
* End of life. Last time buy Nov. 2009.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.1
Oct. 2009
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
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FM25L256B
Power Up to First Access
WREN - Set Write Enable Latch
The FM25L256B is not accessible for a period of
The FM25L256B will power up with writes
time (10 ms) after power up. Users must comply
disabled. The WREN command must be issued prior
with the timing parameter tPU, which is the minimum
to any write operation. Sending the WREN op-code
time from VDD (min) to the first /CS low.
will allow the user to issue subsequent op-codes for
Data Transfer
All data transfers to and from the FM25L256B occur
write operations. These include writing the status
register and writing the memory.
in 8-bit groups. They are synchronized to the clock
Sending the WREN op-code causes the internal
signal (SCK), and they transfer most significant bit
Write Enable Latch to be set. A flag bit in the status
(MSB) first. Serial inputs are registered on the rising
register, called WEL, indicates the state of the latch.
edge of SCK. Outputs are driven from the falling
WEL=1 indicates that writes are permitted.
edge of SCK.
Attempting to write the WEL bit in the status
Command Structure
There are six commands called op-codes that can be
Dissued by the bus master to the FM25L256B. They
are listed in the table below. These op-codes control
Ethe functions performed by the memory. They can be
divided into three categories. First, there are
Dcommands that have no subsequent operations. They
N Sperform a single function such as to enable a write
operation. Second are commands followed by one
E Nbyte, either in or out. They operate on the status
register. The third group includes commands for
M IGmemory transactions followed by address and one or
more bytes of data.
M S 2Table 1. Op-Code Commands
0Name Description
O E VWREN Set Write Enable Latch
5WRDI Write Disable
C D 2RDSR Read Status Register
MWRSR Write Status Register
E FREAD Read Memory Data
W :WRITE Write Memory Data
Op-Code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 0010b
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
T R NE ativeCS
NOFOR AlternSCK
01 2 3 4 5 6 7
SI 0 0 0 0 0 1 1 0
SO Hi-Z
Figure 5. WREN Bus Configuration
Rev. 3.1
Oct. 2009
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Serial Data Bus Timing
FM25L256B
ED/Hold Timing
ND SCS
ME IGNSCK
M SHOLD
O ESO
EC W DPower Cycle Timing
R EVDD
NOFTOR NCS
tHS
tHH
tHH
tHS
25V02tHZ
tLZ
tive: FMVDDmin
t VR
AlternatPU
tVF
tPD
Data Retention (VDD = 2.7V to 3.6V)
Symbol Parameter
TDR Data Retention
@ +75°C
@ +80°C
@ +85°C
Min Units Notes
45 Years
20 Years
10 Years
Rev. 3.1
Oct. 2009
Page 11 of 14
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