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PDF FM25L04B Data sheet ( Hoja de datos )

Número de pieza FM25L04B
Descripción 3V F-RAM Memory
Fabricantes Ramtron 
Logotipo Ramtron Logotipo



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Preliminary
FM25L04B
4Kb Serial 3V F-RAM Memory
Features
4K bit Ferroelectric Nonvolatile RAM
Organized as 512 x 8 bits
High Endurance 100 Trillion (1014) Read/Writes
38 Year Data Retention (@ +75ºC)
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 20 MHz Frequency
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Sophisticated Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
Low Voltage Operation 2.7-3.6V
200 µA Active Current (1 MHz)
3 µA (typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40°C to +85°C
8-pin “Green”/RoHS SOIC and TDFN Packages
Description
The FM25L04B is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM25L04B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been transferred to the device. The next bus cycle
may commence without the need for data polling.
The FM25L04B is capable of supporting 1014
read/write cycles, or a million times more write
cycles than EEPROM.
These capabilities make the FM25L04B ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L04B provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L04B uses the high-speed
SPI bus, which enhances the high-speed write
capability of F-RAM technology. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.3
Feb. 2011
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
Top View
/CS 1
SO 2
/WP 3
VSS 4
8 VDD
7 /HOLD
6 SCK
5 SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
Ordering Information
FM25L04B-G
“Green”/RoHS 8-pin SOIC
FM25L04B-GTR “Green”/RoHS 8-pin SOIC,
Tape & Reel
FM25L04B-DG
“Green”/RoHS 8-pin TDFN
FM25L04B-DGTR “Green”/RoHS 8-pin TDFN,
Tape & Reel
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-F-RAM, (719) 481-7000
www.ramtron.com
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FM25L04B pdf
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Data Transfer
All data transfers to and from the FM25L04B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L04B. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI
RDSR
WRSR
READ
Write Disable
Read Status Register
Write Status Register
Read Memory Data
WRITE Write Memory Data
Op-code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 A011b
0000 A010b
FM25L04B - 4Kb 3V SPI F-RAM
WREN - Set Write Enable Latch
The FM25L04B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
CS
SCK
01 2 3 4 5 6 7
SI 0 0 0 0 0 1 1 0
SO Hi-Z
Figure 5. WREN Bus Configuration
CS
SCK
01 2 3 4 5 6 7
Rev. 1.3
Feb. 2011
SI
SO
00 00 0 10
Hi-Z
Figure 6. WRDI Bus Configuration
0
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FM25L04B arduino
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FM25L04B - 4Kb 3V SPI F-RAM
Serial Data Bus Timing
CS
SCK
SI
SO
tCSU
1/tCK
tH
tSU
tF
tODV
tR
tOH
tCL tCH
tD
tCSH
tOD
/Hold Timing
CS
SCK
HOLD
SO
Power Cycle Timing
tHS
tHH
tHS
tHH
tHZ
tLZ
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min Max Units
tPU VDD(min) to First Access Start
tPD Last Access Complete to VDD(min)
tVR VDD Rise Time
tVF VDD Fall Time
10 - ms
0 - µs
30 - µs/V
100 - µs/V
Notes
1. Slope measured at any point on VDD waveform.
Notes
1
1
Rev. 1.3
Feb. 2011
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