PDF FM25640B Data sheet ( Hoja de datos )

Número de pieza	FM25640B
Descripción	5V F-RAM Memory
Fabricantes	Ramtron
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No Preview Available ! www.DataSheet.co.kr Preliminary FM25640B 64Kb Serial 5V F-RAM Memory Features 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 38 Year Data Retention • NoDelay™ Writes • Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SPI • Up to 20 MHz maximum bus frequency • Direct hardware replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Description The FM25640B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM25640B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM25640B is capable of supporting up to 1012 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM25640B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25640B provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25640B uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Sophisticated Write Protection Scheme • Hardware Protection • Software Protection Low Power Consumption • 250 µA Active Current (1 MHz) • 4 µA (typ.) Standby Current Industry Standard Configuration • Industrial Temperature -40°C to +85°C • 8-pin “Green”/RoHS SOIC (-G) Pin Configuration CS SO WP VSS 1 2 3 4 8 VDD 7 HOLD 6 SCK 5 SI Pin Names /CS /HOLD /WP SCK SI SO VDD VSS Function Chip Select Hold Write Protect Serial Clock Serial Data Input Serial Data Output 5V Ground Ordering Information FM25640B-G “Green”/RoHS 8-pin SOIC FM25640B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.2 Mar. 2011 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-F-RAM, (719) 481-7000 www.ramtron.com Page 1 of 13 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr FM25640B - 64Kb 5V SPI F-RAM Data Transfer All data transfers to and from the FM25640B occur in 8-bit groups. They are synchronized to the clock signal (SCK) and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. The SO output is driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25640B. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by an address and one or more bytes of data. Table 1. Op-code Commands Name Description WREN Set Write Enable Latch WRDI Write Disable RDSR Read Status Register WRSR Write Status Register READ Read Memory Data WRITE Write Memory Data Op-code value 0000_0110b 0000_0100b 0000_0101b 0000_0001b 0000_0011b 0000_0010b WREN - Set Write Enable Latch The FM25640B will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration Rev. 1.2 Mar. 2011 Figure 6. WRDI Bus Configuration 5 of 13 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr Serial Data Bus Timing CS SCK SI SO tCSU 1/tCK tH tSU tF tODV tR tOH FM25640B - 64Kb 5V SPI F-RAM tCL tCH tD tCSH tOD /Hold Timing CS SCK HOLD SO Power Cycle Timing tHS tHH tHS tHH tHZ tLZ Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units tPU VDD(min) to First Access Start tPD Last Access Complete to VDD(min) tVR VDD Rise Time tVF VDD Fall Time 10 - ms 0 - µs 30 - µs/V 100 - µs/V Notes 1. Slope measured at any point on VDD waveform. Notes 1 1 Rev. 1.2 Mar. 2011 11 of 13 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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