FM24V10 Datasheet PDF - Ramtron
| Part Number | FM24V10 | |
| Description | 3V F-RAM Memory | |
| Manufacturers | Ramtron | |
| Logo |  |
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www.DataSheet.co.kr
Pre-Production
FM24V10
1Mb Serial 3V F-RAM Memory
Features
1M bit Ferroelectric Nonvolatile RAM
• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (1014) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 3.4 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz
Device ID and Serial Number
• Device ID reads out Manufacturer ID & Part ID
• Unique Serial Number (FM24VN10)
Low Voltage, Low Power Operation
• Low Voltage Operation 2.0V – 3.6V
• Active Current < 150 µA (typ. @ 100KHz)
• 90 µA Standby Current (typ.)
• 5 µA Sleep Mode Current (typ.)
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC Package
Description
The FM24V10 is a 1-megabit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24V10 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, F-RAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24V10 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24V10 provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The devices are
available in industry standard 8-pin SOIC package
using a familiar two-wire (I2C) protocol. The
FM24VN10 is offered with a unique serial number
that is read-only and can be used to identify a board
or system. Both devices incorporate a read-only
Device ID that allows the host to determine the
manufacturer, product density, and product revision.
The devices are guaranteed over an industrial
temperature range of -40°C to +85°C.
Pin Configuration
NC
A1
A2
VSS
1
2
3
4
8 VDD
7 WP
6 SCL
5 SDA
Pin Name
A1, A2
SDA
SCL
WP
VDD
VSS
Function
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Supply Voltage
Ground
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.0
May 2010
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
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Slave ID
Device Page
Select Select
1 0 1 0 A2 A1 A16 R/W
765 4 3 2 1
0
Figure 4. Slave Address
Addressing Overview
After the FM24V10 (as receiver) acknowledges the
slave address, the master can place the memory
address on the bus for a write operation. The address
requires a 1-bit page select and two bytes. Since the
device uses 17 address bits, the page select bit is the
MSB of the address followed by the remaining 16
address bits. The complete 17-bit address is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch -- either a
newly written value or the address following the last
access. The current address will be held for as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24V10 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFFFh) is reached, the address latch
will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24V10 can begin. For a read operation the
FM24V10 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24V10 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24V10 will end the read operation. For a write
operation, the FM24V10 will accept 8 data bits from
the master then send an acknowledge. All data
transfer occurs MSB (most significant bit) first.
FM24V10 - 1Mb I2C FRAM
Memory Operation
The FM24V10 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24V10 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave address, then a memory
address. The bus master indicates a write operation
by setting the LSB of the slave address (R/W bit) to a
‘0’. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFFFh to 0000h.
Unlike other nonvolatile memory technologies, there
is no effective write delay with F-RAM. Since the
read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge polling,
a technique used with EEPROMs to determine if a
write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8th data bit. The FM24V10 uses no page
buffering.
The memory array can be write-protected using the
WP pin. This feature is available only on FM24V10
and FM24VN10 devices. Setting the WP pin to a
high condition (VDD) will write-protect all addresses.
The FM24V10 will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
Rev. 2.0
May 2010
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FM24V10 electronic component. |
| Information | Total 16 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FM24V10.PDF Datasheet ] | |
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