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PDF NL160120BM27-xx Data sheet ( Hoja de datos )
| Número de pieza | NL160120BM27-xx | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT MONOCHROME LCD MODULE
NL160120BM27-xx
54cm (21.3 Type)
UXGA
PRELIMINARY DATA SHEET
(1st edition)
All information is subject to change without notice.
Please confirm the delivery specification before starting to
design your system.
Document Number: DOD-M- 1316 (1st edition)
Published date: February 2003 CP(N)
1
ã NEC Corporation
2003 All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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NL160120BM27-xx
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display grayscale
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
432.0 (W) × 324.0 (H) mm (typ.)
54 cm (21.3 inches)
a-Si TFT active matrix
256
1600 (H) × 1200 (V) pixels
Sub-pixel vertical stripe
0.090 (W) × 0.270 (H) mm
0.270 (W) × 0.270 (H) mm
457.0 (W) × 350.0 (H) × 25.0 (D) mm (typ.)
(4000) g (typ.)
700:1 (typ.)
At the contrast ratio 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ=2.2): normal axis
Polarizer surface
Polarizer pencil-hardness
Response time
Luminance
Signal system
TBD
TBD H (min.) [by JIS K5400]
Ton + Toff
(25) ms (typ.)
At IBL= 6.0mArms / lamp
800 cd/m2 (typ.)
2 ports LVDS interface (THC63LVD824 THine Electronics, Inc.)
LCR 8-bit signals, Data enable signal (DE), Dot clock (CLK)
Power supply voltage
LCD panel signal processing board: 12.0V
Backlight
Power consumption
Edge light type: 6 cold cathode fluorescent lamps
At checkered flag pattern and IBL= 6.0mArms / lamp
TBD W (typ.)
PRELIMINARY DATA SHEET DOD-M-1316 (1st edition)
5
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NL160120BM27-xx
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 Sequence for LCD panel signal processing board
VDD
Note1
10.8V
0V
Display signals*
Function signals
Note2
0V
ON
5ms < Tr < 80ms
OFF
(9.6V) 10.8V
VDD dip < 20ms
VALID period
10.8V
Toff > 200ms
10ms < t < 35ms
0ms < t < 35ms
* These signals should be measured at the terminal of 100Ω resistor.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a
protection circuit may work, and then this product may not work.
Note2: Display (DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-
and CKB+/-) and function (TxSEL0, TxSEL1) signals must be Low or High-impedance,
exclude the VALID period (See above sequence diagram), in order to avoid that internal
circuits is damaged.
If some of display and function signals of this product are cut while this product is
working, even if the signal input to it once again, it might not work normally. If customer
stops the display and function signals, they should be cut VDD.
Note3: VDD should be (9.6)V or more while VDD ON period.
4.4.2 Sequence for backlight inverter
Display and
function signals
Note1
Note2
VALID period
VDDB
Note1: These are display and function signals for LCD panel signal processing board.
Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of
display and function signals, in order to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-M-1316 (1st edition)
11
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