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PDF NL6448BC33-74 Data sheet ( Hoja de datos )
| Número de pieza | NL6448BC33-74 | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL6448BC33-74
26 cm (10.4 Type)
VGA
DATA SHEET
DOD-PP-0611 (1st edition)
This DATA SHEET is updated document from
PRELIMINARY DOD-PP-0573(2).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PP-0611 (1st edition)
Published date: August 2008 CP(N)
1 © NEC LCD Technologies, Ltd.
2008 All rights reserved.
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NL6448BC33-74
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
211.2 (H) × 158.4 (V) mm
26cm (10.4 inches)
a-Si TFT active matrix
262,144 colors
640 (H) × 480 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.11 (H) × 0.33 (V) mm
0.33 (H) × 0.33 (V) mm
243.0 (W) × 185.1 (H) × 10.5 (D) mm (typ.)
475g (typ.)
800:1 (typ.)
At the contrast ratio ≥ 10:1
• Horizontal: Right side 88° (typ.), Left side 88° (typ.)
• Vertical: Up side 88° (typ.), Down side 88° (typ.)
At DPS= Low or Open: Normal scan
• Viewing angle with optimum grayscale (γ≒ 2.2): normal axis
(Perpendicular)
Clear
3H (min.) [by JIS K5400]
At LCD panel center
50% (typ.) [against NTSC color space]
Ton+Toff (10%←→ 90%)
30ms (typ.)
At IBL= 5.0mArms / lamp
450cd/m2 (typ.)
6-bit digital signals for data of RGB colors,
Dot clock (CLK), Data enable (DE),
Horizontal synchronous signal (Hsync),
Vertical synchronous signal (Vsync)
LCD panel signal processing board: 3.3V or 5.0V
Edge light type: 2 cold cathode fluorescent lamps
Backlight
Power consumption
Replaceable part
• Lamp holder set: Type No. 104LHS49
Recommended inverter (Option)
• Inverter: Type No.: 104PW201
At IBL= 5.0mArms / lamp, Checkered flag pattern
6.6W (typ., Power dissipation of the inverter is not included.)
DATA SHEET DOD-PP-0611 (1st edition)
5
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4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VCC
Note1
3.0V or 4.75V
0V
ON
10μs ≤ Tr < 30ms
Display signals
Function signal
Note2
0V
0ms < t < 35ms
VALID period
NL6448BC33-74
OFF ON
Toff > 50ms
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V in "VCC =
3.3V" or 4.75V in "VCC = 5.0V", a protection circuit may work, and then this product may
not work.
Note2: Display signals (CLK, Hsync, Vsync, DE, DATA (R0 to R5, G0 to G5, B0 to B5)) and
function signal (DPS) must be Low or High-impedance, exclude the VALID period (See
above sequence diagram), in order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. VCC should be cut when
the display and function signals are stopped.
4.4.2 Inverter (Option)
Display signals
Function signal
Note1
Note2
VALID period
VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
DATA SHEET DOD-PP-0611 (1st edition)
11
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