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PDF ADS852 Data sheet ( Hoja de datos )
| Número de pieza | ADS852 | |
| Descripción | 65MHz Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS852 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
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® ADS852
PRELIMINARY INFORMATION
SUBJECT TO CHANGE
WITHOUT NOTICE
TM 14-Bit, 65MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH DYNAMIC RANGE:
High SFDR: 100dB at 20MHz fIN
High SNR: 75dB at 20MHz fIN
q PREMIUM TRACK/HOLD:
High Bandwidth: 1GHz
Low Jitter: 0.25pS rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a high-
bandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This high-
bandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR perfor-
mance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
+VS
ADS852
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
APPLICATIONS
q BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, NMT
q TEST INSTRUMENTATION
q CCD IMAGING
differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further opti-
mizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent dif-
ferential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
Timing Circuitry
CLK
CLK
2Vp-p
2Vp-p
IN
IN
T/H
14-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D13
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
VREF SEL1 SEL2 REFB
OE VDRV
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-1442
Printed in U.S.A. June, 1998
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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TIMING DIAGRAM
Analog In N
N+1 N+2 N+3 N+4 N+5 N+6 N+7
Clock
tD tCONV
tL tH
Data Out
7 Clock Cycles
N–7 N–6 N–5 N–4 N–3 N–2 N–1
t2
N
Data Invalid
t1
SYMBOL
DESCRIPTION
t CONV
tL
tH
tD
t1
t2
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
MIN
15.4
7.6
7.6
3.9
TYP
t CONV / 2
t CONV / 2
3
MAX
1µs
12
UNITS
ns
ns
ns
ns
ns
ns
TABLE, REFERENCE/FULL SCALE RANGE SELECT
DESIRED
FULL SCALE RANGE
4Vp-p (2Vp-p x 2, +16dBm)
3Vp-p (1.5Vp-p x 2, +13dBm)
2Vp-p (1Vp-p x 2, +10dBm)
SEL1
GND
GND
VREF
SEL2
GND
+VS
GND
INTERNAL
VREF
2V
1.5V
1V
For External Reference Operation, tie VREF to +VS, the full scale range will be 2X the reference value. For instance, selecting a 2V External Reference will set
the full scale values of 1.5V to 3.5V for both IN and IN inputs.
®
5 ADS852
Datasheet pdf - http://www.DataSheet4U.net/
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| PDF Descargar | [ Datasheet ADS852.PDF ] | |
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