|
|
PDF AD9633 Data sheet ( Hoja de datos )
| Número de pieza | AD9633 | |
| Descripción | Serial LVDS 1.8 V ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9633 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
Quad, 12-Bit, 80 MSPS/105 MSPS/
125 MSPS, Serial LVDS 1.8 V ADC
AD9633
FEATURES
1.8 V supply operation
Low power: 100 mW per channel at 125 MSPS with scalable
power options
SNR = 71 dB (to Nyquist)
SFDR = 91 dBc (to Nyquist)
DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
signal option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC) with an on-chip sample-and-
hold circuit designed for low cost, low power, small size, and
ease of use. The product operates at a conversion rate of up to
125 MSPS and is optimized for outstanding dynamic performance
and low power in applications where a small package size is
critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
VIN+A
VIN–A
VIN+B
VIN–B
RBIAS
VREF
SENSE
AGND
VIN+C
VIN–C
VIN+D
VIN–D
12
PIPELINE
ADC
DIGITAL
SERIALIZER
12
PIPELINE
ADC
DIGITAL
SERIALIZER
REF
SELECT
1V AD9633
12
PIPELINE
ADC
DIGITAL
SERIALIZER
12
PIPELINE
ADC
DIGITAL
SERIALIZER
VCM
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
D0+A
D0–A
D1+A
D1–A
D0+B
D0–B
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
D0+D
D0–D
D1+D
D1–D
DCO+
DCO–
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
output clock and data alignment and digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9633 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 100 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the AD9253 14-bit quad ADC.
4. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 375 MHz and supports double data
rate (DDR) operation.
5. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9633
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND
AIN2 = −7.0 dBFS
fIN1 = 70.5 MHz, fIN2 = 72.5 MHz
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
POWER SUPPLY REJECTION RATIO (PSRR)1, 4
AVDD
DRVDD
ANALOG INPUT BANDWIDTH, FULL POWER
AD9633-80
AD9633-105
AD9633-125
Temp Min Typ Max Min Typ Max Min Typ Max
25°C 71.7
25°C 71.7
Full 70.0 70.5
25°C 70.3
25°C 69.4
71.7
71.6
70.2 71.0
70.2
69.8
71.8
71.4
70.5 71.1
70.0
69.4
25°C 71.6
25°C 71.5
Full 70.0 70.4
25°C 70.2
25°C 68.4
71.6
71.5
69.5 70.9
69.9
68.7
71.1
71.3
70.5 71.0
69.9
67.4
25°C 11.6
25°C 11.6
Full 11.3 11.5
25°C 11.4
25°C 11.2
11.6
11.6
11.3 11.6
11.3
11.2
11.5
11.5
11.4 11.5
11.3
10.9
25°C 96
25°C 90
Full 76 96
25°C 87
25°C 86
94
89
75 87
91
88
94
91
75 91
86
86
25°C −96 −94 −94
25°C −90 −89 −91
Full
−96 −76
−87 −75
−91 −75
25°C −87 −91 −86
25°C −86 −88 −86
25°C −97 −96 −94
25°C −95 −93 −97
Full
−96 −82
−94 −82
−96 −84
25°C −97 −93 −92
25°C −96 −93 −90
25°C 85 86 87
Full −95 −95 −95
25°C −89 −89 −89
25°C 52 52 52
25°C 75 75 75
25°C 650 650 650
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3 Overrange condition is specified as being 3 dB above the full-scale input range.
4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
Rev. B | Page 4 of 41
5 Page 
AD9633
VIN±x
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
D0–x
D0+x
N–1
tA
tEH
tCPD
N
tEL
Data Sheet
tFCO
tFRAME
tPD tDATA
MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8 N–8 N–8 N–8
Figure 7. Wordwise DDR, One-Lane, 1× Frame, 10-Bit Output Mode
CLK+
SYNC
tSSYNC
tHSYNC
Figure 8. SYNC Input Timing Requirements
Rev. B | Page 10 of 41
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9633.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9630 | Low Distortion 750 MHz Closed-Loop Buffer Amp | Analog Devices |
| AD9631 | Wide Bandwidth Voltage Feedback Op Amps | Analog Devices |
| AD9632 | Wide Bandwidth Voltage Feedback Op Amps | Analog Devices |
| AD9633 | Serial LVDS 1.8 V ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |