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PDF H27U8G8T2B Data sheet ( Hoja de datos )
| Número de pieza | H27U8G8T2B | |
| Descripción | 8 Gbit (1024 M x 8 bit) NAND Flash | |
| Fabricantes | Hynix | |
| Logotipo |  |
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Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash
8 Gb NAND Flash
H27U8G8T2B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.0 / Jul. 2008
1
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
1
www.DataSheet.co.kr
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash
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Figure 1 : Logic Diagram
IO7 - IO0
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ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1 : Signal Names
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Figure 2 : 48-TSOP1 Contact, x8 Device
Rev 0.0 / Jul. 2008
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
1
www.DataSheet.co.kr
Preliminary
H27U8G8T2B Series
8 Gbit (1024 M x 8 bit) NAND Flash
3.3 Page Program
The device is programmed by page. Only a single partial or complete page programming operation within the same page,
without an intervening erase operation, is allowed
The addressing must be done in sequential order in a block. A page program cycle consists of a serial data loading period
in which up to 4,224 data bytes may be loaded into the data register, followed by a non-volatile memory programming
period where the loaded data are programmed into the appropriate cells.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by five address cycles
input and then zero or more serial data input cycles. The words other than those to be programmed do not need to be
loaded. The device supports random data input in a page. The column address of next data, which will be entered, may
be changed to the address which follows random data input command (85h). Random data input may be operated multiple
times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously en-
tering the serial data will not initiate the programming process. The internal write state controller automatically executes
the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once
the program process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are accepted while programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O 0) may be tested to check for fails in the program operation. The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register re-
mains in Read Status command mode until another valid command is written to the command register. Figure 15 and Fig-
ure 17 detail the sequence.
3.4 Multiplane Page Program
Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 8,448 bytes of data may be
loaded into the data register, followed by a non-volatile memory programming period when the loaded data are pro-
grammed into the appropriate cells. The serial data loading period begins by inputting the Serial Data Input command
(80h), followed by the five address cycles input and then zero or more serial data for the 1st page. Address for this page
must be within 1st plane (A<20>=0) and A<19:13> and A<30:21> must be fixed low. Data of 1st page other than those
to be programmed do not need to be loaded. The device supports random data input exactly like a normal page program
operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device goes busy for a
short time (tDBSY). Once it has returned ready, 81h command must be issued, followed by page address cycles and zero
or more serial data input cycles. Address for this page must be within 2nd plane (A<20>=1) and A<19:13> and A<30:21>
must be the valid addresses. The data of 2nd page other than those to be programmed do not need to be loaded. Program
Confirm command (10h) makes parallel programming of both pages start. User can check operation status by R/B pin or
read status register command, as if it were a normal page program; status register command is also available during Dum-
my Busy time (tDBSY).
In case of fail in 1st or 2nd page program, fail bit of status register will be set: the device supports pass/fail status of
each plane (IO0: total; IO1: plane0; IO2: plane1). Figure 16 details the sequence.
3.5 Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished giving 3 address cycles initiated
by an Erase Setup command (60h). Only addresses A20 to A30 are valid while A13 to A19 are ignored. The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise condi-
tions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-
verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase op-
eration is completed, the Write Status Bit (I/O 0) may be checked.
Figure 18 details the sequence.
Rev 0.0 / Jul. 2008
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