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PDF H5MS1262EFP Data sheet ( Hoja de datos )
| Número de pieza | H5MS1262EFP | |
| Descripción | 128M (8Mx16bit) Mobile DDR SDRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O
Specification of
128M (8Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.1 / July. 2009
1
1 page  
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Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
The Hynix H5MS1262EFP series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
The Hynix H5MS1262EFP series is available in the following package:
- 60Ball FBGA [size: 8mm x 10mm, t=1.0mm max]
128Mb Mobile DDR SDRAM ORDERING INFORMATION
Part Number
Clock Frequency
Organization Interface
Temp.
Package
H5MS1262EFP-J3E 166MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-K3E 133MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-L3E 100MHz(CL3) / 66MHz(CL2)
4banks x 2Mb x 16
H5MS1262EFP-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-K3M 133MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-L3M 100MHz(CL3) / 66MHz(CL2)
Extended
Temp. : -25oC
~ 85oC
60Ball Lead
Free
LVCMOS
Mobile Temp.
: -30oC ~
85oC
60Ball Lead
Free
Rev 1.1 / July. 2009
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5 Page 
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Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
REGISTER DEFINITION II
Extended Mode Register Set (EMRS) for Mobile DDR SDRAM
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 DS 0 0
PASR
DS (Drive Strength)
A6 A5
Drive
Strength
0 0 Full
0 1 Half (Default)
1 0 Quarter
1 1 Octant
Rev 1.1 / July. 2009
PASR (Partial Array Self Refresh)
A2 A1 A0 Self Refresh Coverage
0 0 0 All Banks (Default)
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
1 1 0 One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
1 1 1 Reserved
11
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