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PDF NL6448AC63-01 Data sheet ( Hoja de datos )
| Número de pieza | NL6448AC63-01 | |
| Descripción | LCD Module | |
| Fabricantes | NEC | |
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DOD - M - 0412 1/53
TFT COLOR LCD MODULE
NL6448AC63-01
51.0cm (20.1 Type)
VGA
SPECIFICATIONS
(5th Edition)
PRELIMINARY
All information is subject to change without notice.
2001 All rights reserved.
Published by
1st Engineering Department
Color LCD Division
Display Device Operations Unit
NEC Electron Devices
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1. OUTLINE
1.1 STRUCTURE AND PRINCIPLE
NL6448AC63-01 module is composed of the amorphous silicon thin film transistor liquid crystal
display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT (Thin Film Transistor) array
and a backlight unit.
The a-Si TFT LCD panel structure is injected liquid crystal material into a narrow gap between the TFT
array glass substrate and a color-filter glass substrate.
Color (Red, Green, Blue) data signals from a host system (e.g. PC, signal generator, etc.) are modulated
into best form for active matrix system by a signal processing board, and sent to the driver LSIs which
drive the individual TFT arrays.
The TFT array as an electro-optical switch regulates the amount of transmitted light from the backlight
assembly, when it is controlled by data signals. Color images are created by regulating the amount of
transmitted light through the TFT array of red, green and blue dots.
1.2 APPLICATIONS
• Multimedia monitor
• TV monitor
• Display terminal for control system
1.3 FEATURES
• High luminance
• Wide viewing angle
• High contrast
• Low reflection
• 8-bit digital RGB signals
• Select function of best viewing angle
• Reversible-scan direction
• Direct light type
• Replaceable backlight unit and inverter
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4.4 SUPPLY VOLTAGE SEQUENCE
4.4.1 Sequence for LCD panel signal processing board
VCC 3.0V
Note1 0V
Display
signals
Note2
ON
Tr < 30ms
0ms < t < 35ms
VALID period
DOD - M - 0412 11/53
OFF
Toff > 50ms
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V, a
protection circuit may work, and then this product may not work.
Note2: Display signals (CLK, Hsync, Vsync, DE, MVA, R0 to R7, G0 to G7, B0 to B7, R/L and
U/D) must be Low or High-impedance, exclude the VALID period (See above sequence
diagram), in order to avoid that internal circuits is damaged.
If some of display signals of this product are cut while this product is working, even if the
signal input to it once again, it might not work normally. If customer stop display signals,
they should be cut VCC.
4.4.2 Sequence for backlight inverter
Display
signals
Note1
Note2
VALID period
12.0V
VDDB 10.8V
ViBCH
BRTC
Note3 tr
t > 0 ms
Note1: These are the display signals for LCD panel signal processing board.
Note2: The backlight power voltage (VDDB) should be inputted within the valid period of display
signals, in order to avoid unstable data display.
Note3: The tr should be less than 800ms when BRTC terminal [Socket: CN202, Pin No.: 4] (See
'4.5.2 Backlight inverter'.) is Open.
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| PDF Descargar | [ Datasheet NL6448AC63-01.PDF ] | |
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