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PDF NTD4965N Data sheet ( Hoja de datos )
| Número de pieza | NTD4965N | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTD4965N
Power MOSFET
30 V, 68 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
C(Nuorrteen1t)RqJA
TA = 25°C
TA = 100°C
VDSS
VGS
ID
30
±20
17.8
12.6
V
V
A
Power
Dissipation
(Note 1)
RqJA
TA = 25°C
PD
2.6 W
Continuous Drain
C(Nuorrteen2t)RqJA
Power
Dissipation
(Note 2)
RqJA
Steady
State
TA = 25°C
TA = 100°C
TA = 25°C
ID
PD
13.0 A
9.2
1.39 W
Continuous Drain
C(Nuorrteen1t)RqJC
TC = 25°C
TC = 100°C
ID
68 A
48
Power
Dissipation
(Note 1)
RqJC
TC = 25°C
PD
38.5 W
Pulsed Drain
Current
tp=10ms TA = 25°C
IDM
248 A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
IDmaxPkg
TJ,
TSTG
IS
dV/dt
76
−55 to
+175
35
6.0
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V,
IL = 28 Apk, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
TL
39 mJ
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
4.7 mW @ 10 V
10 mW @ 4.5 V
D
ID MAX
68 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 23
1 23
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4965N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
www.Dat©aSSheemeitc4oUnd.uncetotr Components Industries, LLC, 2011
April, 2011 − Rev. 1
1
Publication Order Number:
NTD4965N/D
1 page  
NTD4965N
TYPICAL PERFORMANCE CURVES
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
0
TJ = 25°C
VGS = 0 V
Ciss
Coss
Crss
5 10 15 20 25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
30
1000
100
VDD = 15 V
ID = 15 A
VGS = 10 V
td(off)
10 tf
tr
td(on)
11
1000
10
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
100
10 ms
10
100 ms
1 ms
10 ms
1 0 V < VGS < 10 V
Single Pulse
0.1
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
0.01
0.01
PACKAGE LIMIT
0.1 1
dc
10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10
9 QT
8
7
6
5
4 Qgs
Qgd
3 ID = 30 A
2 TJ = 25°C
1
VDD = 15 V
VGS = 10 A
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage vs. Total Charge
30
VGS = 0 V
25
TJ = 125°C
20
TJ = 25°C
15
10
5
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
40
36 ID = 28 A
32
28
24
20
16
12
8
4
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
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