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PDF KK74HC574A Data sheet ( Hoja de datos )
| Número de pieza | KK74HC574A | |
| Descripción | Octal 3-State Noninverting D Flip-Flop | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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TECHNICAL DATA
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The KK74HC574A is identical in pinout to the LS/ALS574. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The OE input does not affect the states of the flip-flops,
but when OE is high, all device outputs are forced to the high-impedance
state; thus, data may be stored even when the outputs are not enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
KK74HC574A
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SOIC
ORDERING INFORMATION
KK74HC574AN
Plastic DIP
KK74HC574ADW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
DATA
INPUTS
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
CLOCK 11
1
OE
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
PIN 20=VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 V CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CLOCK
FUNCTION TABLE
Inputs
OE Clock
Output
DQ
L
L
L L,H,
HX
H= high level
L = low level
X = don’t care
Z = high impedance
HH
LL
X no
change
XZ
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KK74HC574A
CLOCK
Q
tr tf
90%
50%
10%
tw
1/fmax
tPLH
50% 90%
10%
tTLH
tTHL
VCC
GND
t PHL
OE 50%
t PZL
Q
tPZH
Q
50%
50%
t PLZ
tPHZ
10%
90%
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
D
CLOCK
VALID
50%
t su th
50%
Figure 3. Switching Waveforms
VCC
GND
VCC
GND
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*
CL
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1k
*
CL
Connect to VCC when
testing tPLZ and tPZL
Connect to GND when
testing tPHZ and tPZH
* Includes all probe and jig capacitance
Figure 4. Test Circuit
* Includes all probe and jig capacitance
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CLOCK
OE
D
CQ
D
CQ
D
CQ
D
CQ
D
CQ
D
CQ
D
CQ
D
CQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet KK74HC574A.PDF ] | |
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