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PDF KK74HC4051A Data sheet ( Hoja de datos )
| Número de pieza | KK74HC4051A | |
| Descripción | Analog Multiplexer Demultiplexer | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KK74HC4051A (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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TECHNICAL DATA
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
KK74HC4051A
The KK74HC4051A utilize silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from VCC
to VEE).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input.When the Enable pin is high, all analog switches
are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LS/ALSTTL outputs.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V
• Low Noise
ORDERING INFORMATION
KK74HC4051AN Plastic
KK74HC4051ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Single-Pole, 8-Position Plus Common Off
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
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FUNCTION TABLE
Control Inputs
Enable
Select
CBA
L LLL
L LLH
L LHL
L LHH
L HLL
L HLH
L HHL
L HHH
H XXX
X = don’t care
ON
Channels
X0
X1
X2
X3
X4
X5
X6
X7
None
1
1 page  
KK74HC4051A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
VCC
Symbol
Parameter
Test Conditions
V
BW Maximum On- fin=1 MHz Sine Wave
Channel
Adjust fin Voltage to Obtain 0 dBm at VOS
Bandwidth or Increase fin Frequence Until dB Meter
Minimum
Reads -3 dB
Frequency
Response
RL =50 Ω, CL=10 pF
(Figure 5)
2.25
4.50
6.00
- Off-Channel fin= Sine Wave
Feedthrough
Adjust fin Voltage to Obtain 0 dBm at VIS
Isolation
(Figure 6)
fin = 10 kHz, RL =600 Ω, CL=50 pF
2.25
4.50
6.00
fin = 1.0 MHz, RL =50 Ω, CL=10 pF
2.25
4.50
6.00
- Feedthrough VIN≤ 1 Mhz Square Wave (tr = tf = 6 ns)
Noise, Channel Adjust RL at Setup so that IS= 0 A Enable =
Select Input to GND
Common O/I
(Figure 7)
RL =600 Ω, CL=50 pF
2.25
4.50
6.00
RL =10 Ω, CL=10 pF
2.25
4.50
6.00
THD
Total Harmonic
Distortion
(Figure 15)
fin= 1 kHz, RL =10 kΩ, CL=50 pF
THD = THDMeasured - THDSource
VIS =4.0 VPP sine wave
VIS =8.0 VPP sine wave
VIS =11.0 VPP sine wave
2.25
4.50
6.00
* Limits not tested. Determined by design and verified by qualification.
VEE Limit*
V 25 °C Unit
MHz
-2.25
-4.50
-6.00
80
80
80
dB
-2.25
-4.50
-6.00
-2.25
-4.50
-6.00
-50
-50
-50
-40
-40
-40
mVPP
-2.25
-4.50
-6.00
25
105
135
-2.25
-4.50
-6.00
35
145
190
%
-2.25
-4.50
-6.00
0.10
0.08
0.05
Figure 1. On Resistance Test Set-Up
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KK74HC4051A.PDF ] | |
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