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KK74HC112A fiches techniques PDF

KODENSHI KOREA - Dual J-K Flip-Flop

Numéro de référence KK74HC112A
Description Dual J-K Flip-Flop
Fabricant KODENSHI KOREA 
Logo KODENSHI KOREA 





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KK74HC112A fiche technique
TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Performance Silicon-Gate CMOS
KK74HC112A
The KK74HC112A is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC112AN Plastic
KK74HC112AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
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FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
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