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PDF Q32M210 Data sheet ( Hoja de datos )
| Número de pieza | Q32M210 | |
| Descripción | Precision Mixed-Signal 32-bit Microcontroller SPI/SQI interface | |
| Fabricantes | ON Semiconductor | |
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Q32M210
Precision Mixed-Signal
32-bit Microcontroller
Introduction
Q32M210 is a precision, mixed−signal 32−bit microcontroller. The
microcontroller is built on the high performance ARM® Cortext−M3
processor.
The microcontroller incorporates a highly configurable sensor
interface designed to work directly with a wide range of sensors
having multiple characteristics, including specialized electrochemical
sensors. The sensor interface includes dual programmable gain
amplifiers, dual 16−bit Analog−to−Digital converters, triple 10−bit
Digital−to−Analog converters (for voltage waveform generation and
other applications) and three uncommitted, low−noise opamps with
configurable signal multiplexing. Flexible connectivity to external
non−volatile memory, personal computers, wireless devices, LCD
displays and a wide range of other peripherals is enabled by several
digital interfaces including I2C, USB (2.0 full−speed compliant) and a
high−speed SPI/SQI interface.
The microcontroller features flexible clocking options as well as
intelligent failure monitoring of power and application interruptions
required by high performance, portable, battery operated applications.
All necessary clocks including an internal oscillator, real−time clock
and a dedicated clock for USB operation are available on−chip
(external crystals required for RTC and USB).
An embedded power management unit, which incorporates several
low power modes, allows application developers to minimize both
standby and active power under a wide range of operating conditions.
The ultra−low sleep current makes the microcontroller ideal for
applications that remain inactive for long periods of time.
A large on−chip non−volatile flash memory (256 kB) combined
with on−chip SRAM (48 kB) supports complex applications and
simplifies application development. The flash contains built−in
hardware error checking and correction (ECC) for application
reliability. Additionally, a configurable DMA unit which supports
independent peripheral−to−memory, memory−to−memory, and
memory−to− peripheral channels provides flexible, low power data
transfers without processor intervention.
A suite of industry−standard development tools, hands−on training
and full technical support are available to reduce design cycle time and
speed time−to−market.
• The Q32M210 Microcontroller is Pb−Free, Halogen Free/BFR Free
and RoHS Compliant
http://onsemi.com
TLLGA−140
DUAL−ROW
CASE 513AL
MARKING DIAGRAM
Q32M210
AWLYYWWG
Q32M210 = Device Code
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 50 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
April, 2011 − Rev. 5
1
Publication Order Number:
Q32M210/D
1 page  
Q32M210
minimum voltage of 1.8 V. No external power management
circuitry is required to support flash access.
VADC
The VADC Analog Supply Regulator (VADC) provides a
nominal 1.8 V power supply for the ADCs and PGAs. This
separate supply ensures noise immunity between the analog
and digital subsystems. VADC may be enabled or disabled
as required to save power.
VDBL
The VDBL Charge Pump (VDBL) provides a nominal
3.5 V power supply under any normal operating range
battery voltage. VDBL is powered from the dedicated
on−chip Charge Pump Supply Regulator (VCP). This
separate supply ensures noise immunity between VDBL, the
other on−chip power supplies as well as from the battery.
VDBL is normally used to power an LCD segment display
and associated backlight or any other external devices
requiring a fixed, high voltage rail. VDBL may also be used
to power the sensor interface. This is useful when a fixed,
higher voltage rail is required for the sensor interface
compared to the battery voltage.
ILV
An on−chip programmable current sink (ILV) is available
to adjust the amount of current from VDBL through an LED
backlight. In a typical configuration an LED is connected
between VDBL and ILV. The application controls the LED
brightness by adjusting the current setting.
VREF Precision Voltage Reference
The device provides an on−chip low−temperature drift
reference voltage, VREF. VREF is factory calibrated to 0.9 V.
VREF is available externally and is also connected internally
to the ADCs and DACs for their reference voltages.
I/O Pin Supplies
The device’s I/O pins are powered from multiple supplies.
This allows the device to match its I/O voltage levels to
external devices as required.
One bank of digital I/O pins is powered from VDDIO0.
The voltage applied to VDDIO0 determines the logic level
for the associated pins. A second bank of mixed signal I/O
pins is powered from VDDIO1.
The voltage applied to VDDIO1 determines the digital
logic level for the associated pin. When the mixed signal I/O
pins are configured for LCD operation, VDDIO1 must be at
or above VLCD supply voltage for proper operation.
The USB pins USBDP and USBDN are powered directly
from VDDUSB.
The IF5 pins are powered directly from VBATA.
All analog signal pins are powered directly from VBATA.
Power Supervisor, Power−on Reset, and Brown−Out
Protection
The device contains a dedicated hardware power
supervisor for monitoring the supply voltages. The power
supervisor ensures the device operates deterministically,
and without any unexpected behavior during all supply
conditions.
The power supervisor releases the internal Power−on
Reset (POR) when the supply voltage on VBAT exceeds the
minimum threshold for proper operation. The release of
POR enables the VDDD Digital Supply Regulator. The
power supervisor continues to monitor VBAT. If VBAT
drops below the minimum threshold for proper operation the
device is reset.
No external circuitry is required for proper device startup.
All required start−up delays and reset thresholds are
generated on−chip. The RSTB pin may be left floating
during startup.
The ARM Cortex−M3 Processor and all digital subsystem
components including the flash, SRAM, and peripherals
will operate reliability down to a nominal VDDD supply
voltage of 1.8 V. In run mode, the power supervisor
continually monitors VDDD. If VDDD drops below the
minimum threshold for proper operation the device is reset.
The power supervisor is automatically disabled in sleep
mode and standby mode to save power.
Supply Monitor
During run mode, the actual voltage levels for VBAT,
VBATA, VREF, and VADC can be measured through either
one of the ADC channels. This allows the application to
determine the actual supply levels and appropriately handle
the graceful shutdown of the system when the battery
approaches its useful end−of−life. Additional voltages may
be monitored through one of the auxiliary inputs.
In a system configuration where the sensor interface may
be supplied from either the battery or the VDBL Charge
Pump, the application can use the measured VBAT voltage
level to determine whether to enable VDBL or continue to
supply the sensor interface from the battery.
External Reset
The device contains an external reset pin (RSTB). When
RSTB is asserted, the digital subsystem including the ARM
Cortex−M3 Processor is reset. The real−time clock counters
are not reset by an external reset. The RSTB function is only
available in run mode. Asserting the RSTB pin during the
Power−on Reset sequence will prevent the ARM
Cortex−M3 Processor from running. The system will be held
in reset until the pin is released. RSTB can be left floating.
System Wakeup
Wakeup occurs when the device is switched from standby
mode or sleep mode into run mode. This can be
accomplished through one of the wakeup mechanisms. The
wakeup controller allows for up to four external events to
wake up the system. Two IF5 pins (IF5.0, IF5.1) will wakeup
the system when a High−to−Low transition is detected. Two
IF5 pins (IF5.2, IF5.3) will wakeup the system when a Low−
to−High transition is detected. The RTC Alarm can also be
configured to wakeup the system at a predetermined time.
http://onsemi.com
5
5 Page 
Q32M210
Table 1. PIN DEFINITIONS
Pin
140
TLLGA
Pin Name
(Note 6)
Type
(Note 1)
Direction
(Note 2)
Pull−up /
Pull−Down
(Note 3)
Pin Power
Supply
Primary
(Note 4)
Function
Alternate 1 Alternate 2
B4 USBDP
D
I/O
−
VDDUSB
USBDP
−
−
A5 USBDN
D
I/O
−
VDDUSB
USBDN
−
−
B44 SCL D I/O
PU VDDIO0
SCL
−
−
A51 SDA
D
I/O
PU VDDIO0
SDA
−
−
A48 IF0.0
D
I/O
PU
VDDIO0
SPI0_CLK
GPIO32
−
A53 IF0.1
D
I/O
PU
VDDIO0
SPI0_CS
GPIO33
USRCLK0
A57 IF0.2
D
I/O
PU
VDDIO0
SPI0_SI
GPIO34
USRCLK1
A56 IF0.3
D
I/O
PU
VDDIO0
SPI0_SO
GPIO35
USRCLK2
A47 IF1.0
D
I/O
PU
VDDIO0
SPI1_CLK
GPIO36
PCM_CLK
B39 IF1.1
D
I/O
PU
VDDIO0
SPI1_CS
GPIO37
PCM_FR
A52 IF1.2
D
I/O
PU
VDDIO0
SPI1_SI
GPIO38
PCM_SI
B45 IF1.3
D
I/O
PU
VDDIO0
SPI1_SO
GPIO39
PCM_SO
B48 IF2.0
D
I/O
PU
VDDIO0
UART0_TX
GPIO40
−
A49 IF2.1
D
I/O
PU
VDDIO0
UART0_RX
GPIO41
−
B41 IF3.0
D
I/O
PU
VDDIO0
UART1_TX
GPIO42
SQI_SIO[2]
A54 IF3.1
D
I/O
PU
VDDIO0
UART1_RX
GPIO43
SQI_SIO[3]
A2 IF4.0
M
I/O
PD
VDDIO1
GPIO0
COM0
−
A1 IF4.1
M
I/O
PD
VDDIO1
GPIO1
COM1
−
B1 IF4.2
M
I/O
PD
VDDIO1
GPIO2
COM2
−
A76 IF4.3
M
I/O
PD
VDDIO1
GPIO3
COM3
−
B64 IF4.4
M
I/O
PD
VDDIO1
GPIO4
SEG0
−
A75 IF4.5
M
I/O
PD
VDDIO1
GPIO5
SEG1
−
B63 IF4.6
M
I/O
PD
VDDIO1
GPIO6
SEG2
−
A74 IF4.7
M
I/O
PD
VDDIO1
GPIO7
SEG3
−
A72 IF4.8
M
I/O
PD
VDDIO1
GPIO8
SEG4
−
B61 IF4.9
M
I/O
PD
VDDIO1
GPIO9
SEG5
−
B60 IF4.10
M
I/O
PD
VDDIO1
GPIO10
SEG6
−
A70 IF4.11
M
I/O
PD
VDDIO1
GPIO11
SEG7
−
B59 IF4.12
M
I/O
PD
VDDIO1
GPIO12
SEG8
−
A69 IF4.13
M
I/O
PD
VDDIO1
GPIO13
SEG9
−
B58 IF4.14
M
I/O
PD
VDDIO1
GPIO14
SEG10
−
A68 IF4.15
M
I/O
PD
VDDIO1
GPIO15
SEG11
−
B57 IF4.16
M
I/O
PD
VDDIO1
GPIO16
SEG12
−
A67 IF4.17
M
I/O
PD
VDDIO1
GPIO17
SEG13
−
B56 IF4.18
M
I/O
PD
VDDIO1
GPIO18
SEG14
−
A66 IF4.19
M
I/O
PD
VDDIO1
GPIO19
SEG15
−
B55 IF4.20
M
I/O
PD
VDDIO1
GPIO20
SEG16
−
A65 IF4.21
M
I/O
PD
VDDIO1
GPIO21
SEG17
−
1. Types: D – Digital, M – Mixed signal, A – Analog, S – Supply
2. Direction: I − Input, O – Output, I/O – Input or Output
3. PU – Pull−up, PD – Pull−down. Most Pull−up and Pull−downs may be disconnected in firmware
4. Primary function is the power−on default. Alternate functions may be selected in firmware
5. TEST must be connected to VSS for proper device operation
6. All pins with the same name must be shorted together for proper device operation
7. IF5.0 can be used as an analog external input to programmable gain amplifiers
Alternate 3
−
−
−
−
−
−
SQI_SIO[1]
SQI_SIO[0]
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
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11
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| Páginas | Total 50 Páginas | |
| PDF Descargar | [ Datasheet Q32M210.PDF ] | |
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