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PDF ICE3PCS02G Data sheet ( Hoja de datos )
| Número de pieza | ICE3PCS02G | |
| Descripción | Standalone Power Factor Correction (PFC) Controller | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Version 2.0, 5 May 2010
CCM-PFC
ICE3PCS02G
www.DataSheet4U.net
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM)
Power Management & Supply
1 page  
CCM-PFC
Preliminary Datasheet ICE3PCS02G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration
ratings. Therefore a series resistor (RCS) of around 50Ω
is recommended in order to limit this current into the IC.
Pin Symbol
1 ISENSE
2 GND
3 ICOMP
4 FREQ
5 OVP
6 VSENSE
7 VCC
8 GATE
Function
Current Sense Input
IC Ground
Current Loop Compensation
Switching Frequency Setting
Over Voltage Protection
Bulk Voltage Sense
IC Supply Voltage
Gate Drive
GND (IC Ground)
The ground potential of the IC.
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control
loop. The capacitor which is connected at this pin
integrates the output current of OTA6 and averages the
current sense signal.
FREQ (Frequency Setting)
This pin allows the setting of the operating switching
frequency by connecting a resistor to ground. The
frequency range is from 21kHz to 250kHz.
Package PG-DSO-8
OVP
A resistive voltage divider from bulk voltage to GND
can set the over voltage protection threshold. This
additional OVP is able to ensure system safety
operation.
ISENSE
GND
ICOMP
FREQ
P-DSO-8
GATE
VCC
VSENSE
OVP
VSENSE
VSENSE is connected via a resistive divider to the bulk
voltage. The voltage of VSENSE relative to GND
represents the output voltage. The bulk voltage is
monitored for voltage regulation, over voltage
protection and open loop protection.
VCC
VCC provides the power supply of the ground related
to IC section.
Figure 1 Pin Configuration (top view)
GATE
GATE is the output for driving the PFC MOSFET.Its
gate drive voltage is clamped at 15V (typically).
1.2 Pin Functionality
ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (RSHUNT). This is the input signal
for the average current regulation in the current loop. It
is also fed to the peak current limitation block.
During power up time, high inrush currents cause high
negative voltage drop at RSHUNT, driving currents out of
pin 1 which could be beyond the absolute maximum
Version 2.0
5 5 May 2010
5 Page 
Ramp Profile
Ave(Iin) at ICOMP
CCM-PFC
ICE3PCS02G
Functional Description
immediately and maintained in off state for the current
PWM cycle. The signal TOFFMIN resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Gate
Drive
t
Figure 9
Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 3
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of TOFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
TOFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle DOFF.
Figure 10 shows the timing diagrams of the TOFFMIN and
the gate waveforms.
Clock
V (1)
C,ref
Toff_min 600 ns
PWM Cycle
Toff _min
600ns
Peak current limit
Current
limit Latch
RQ
SQ
Current loop
PWM on signal
PWM on
Latch
RQ
SQ
High = turn on Gate
Figure 11
PWM LOGIC
3.8 System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
3.8.1 Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 1 (ISENSE)
reaches -0.4V. This voltage is amplified by a factor of -
2.5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 12. A deglitcher with
200ns after the comparator improves noise immunity to
the activation of this protection.
Vram p
GATE
Ramp
Released
V(1)
c,ref
is
a
function
of
V ICOMP
Figure 10
Ramp and PWM waveforms
t
Full-wave
rectifier
ISENSE
RCS
Rshunt
Iin
SGND
G=-2.5
AO2
200ns
PCL
C5
1V
3.7 PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse TOFFMIN, are
designed to meet a maximum duty cycle DMAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
Figure 12 Peak Current Limit (PCL)
3.8.2 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently VOUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage VIN for
normal operation. It is implemented using comparator
Version 2.0
11 5 May 2010
11 Page | ||
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| PDF Descargar | [ Datasheet ICE3PCS02G.PDF ] | |
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