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PDF ICE3DS01L Data sheet ( Hoja de datos )
| Número de pieza | ICE3DS01L | |
| Descripción | Off-Line SMPS Current Mode Controller | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Datasheet, V2.0, 15 May 2003
PWM-FF IC
ICE3DS01L
ICE3DS01LG
Off-Line SMPS Current Mode
www.DataSheet4U.net
Controller with integrated 500V
Startup Cell
Power Management & Supply
Never stop thinking.
1 page  
F3
ICE3DS01L/LG
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with P-DIP-8-6 1.2 Pin Configuration with P-DSO-8-8
Pin Symbol Function
1 SoftS Soft-Start
2 FB Feedback
3 CS Current Sense
4 HV High Voltage Input
5 HV High Voltage Input
6 Gate Driver Stage Output
7 VCC Controller Supply Voltage
8 GND Controller Ground
Pin Symbol Function
1 SoftS Soft-Start
2 FB Feedback
3 CS Current Sense
4 Gate Driver Stage Output
5 HV High Voltage Input
6 N.C. Not connected
7 VCC Controller Supply Voltage
8 GND Controller Ground
Package P-DIP-8-6
Package P-DSO-8-8
SoftS
1
FB 2
CS 3
HV 4
8 GND
7 VCC
6 Gate
5 HV
SoftS
1
FB 2
CS 3
Gate
4
8 GND
7 VCC
6 N.C.
5 HV
Figure 1 Pin Configuration P-DIP-8-6(top view)
Note: Pin 4 and 5 are shorted within the DIP
package.
Figure 2
Pin Configuration P-DSO-8-8(top view)
Version 2.0
5
15 May 2003
5 Page 
F3
ICE3DS01L/LG
Functional Description
3.5 Current Limiting
PWMLatch Latched Off
FF1 Mode
Spike
Blanking
190ns
Current Limiting
1.66V
C11
Propagation-Delay
Compensation
C10 Vcsth Leading
Edge
PWM-OP
Blanking
220ns
&
G10 C12
0.257V
Active Burst
Mode
10k
D1
1pF
CS
Figure 10 Current Limiting
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor RSense . By means of RSense the source current
is transformed to a sense voltage VSense which is fed
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage Vcsth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a
short winding in the transformer or the secondary diode
is shorten. To ensure that there is no accidentally
entering of the Latched Mode by the comparator C11 a
spike blanking with 190ns is integrated in the output
path of comparator C11.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
3.5.1
Leading Edge Blanking
VSense
Vcsth
tLEB = 220ns
t
Figure 11 Leading Edge Blanking
Each time when the external Power Switch is switched
on a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. To avoid a premature
termination of the switching pulse this spike is blanked
out with a time constant of tLEB = 220ns. During that
time there can’t be an accidentally switch off of the gate
drive.
3.5.2 Propagation Delay Compensation
In case of overcurrent detection the shut down of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 12).
ISense
Ipeak2
Ipeak1
ILim it
S ig n a l2
IO vershoot2
S ig n a l1
tPropagation Delay
IO v e rs ho o t1
t
Figure 12 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
Version 2.0
11
15May 2003
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ICE3DS01L.PDF ] | |
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